Analog computing platforms have been a popular and promising research area that suggest efficient ways of computation compared to its digital counterparts. Memristor based crossbars drew attention by computing the vector-matrix calculation intensive tasks such as Artificial Intelligence (AI) and Machine Learning (ML) in one time step. Although they provide an energy efficient way of computing these tasks, analog computation in general suffers from non-idealities and systematic errors in the circuitry, which could degrade the performance and accuracy significantly. One of the issues is the random offset associated with the op-amps in the system resulting from the process and mismatch variations. In this paper, a novel technique is offered to reduce the negative effects of the random offset and increase the output accuracy. This newly proposed system uses minimum extra circuitry and additional power consumption and only requires the crossbar to be enlarged by two extra rows. The intrinsic issue of the analog crossbars, interconnect parasitics, must be incorporated into the problem, and a way to separate the offset and wire resistance issues from each other is offered. The functionality of the system has been shown with a case study in the results section where the op-amps have$\sigma_{offset}=3mV$. The effectiveness of the offered technique demonstrates a 6× better accuracy with the mitigation of the offset problem. The proposed method can be used in memristor and other analog crossbars to achieve a greater performance and thus improve their competitiveness.

Over the last decade, Gaussian processes (GPs) have become popular in the area of machine learning and data analysis for their flexibility and robustness. Despite their attractive formulation, practical use in large-scale problems remains out of reach due to computational complexity. Existing direct computational methods for manipulations involving large-scale$n\times n$covariance matrices require$O(n^{3})$calculations. In this work, we present the design and evaluation of a simulated computing platform for exact GP inference, that achieves true model parallelism using memristive crossbars. To achieve a one-shot solution, a linear equation solver and a vector-matrix multiplication solver crossbar configurations are used together, reducing the number of operations from$O(n^{3})$to$O(n)$. The transistor level op-amps, ADC models for quantization, circuit and interconnect parasitics, together with the finite memristor precision are incorporated into the system simulation. The analog system resulted in %1.51 mean error and %2.93 average variance error in solving a nonlinear regression problem. The proposed method achieved 9× to 144× better energy efficiency compared to TPU and 7× compared to a custom analog linear regression solver.

Determining the dominant eigenvector of matrices and graphs is one of the most fundamental tasks in many machine learning problems, including spectral clustering, Hyperlink Induced Topic Search (HITS), Markov Chains, PageRank and eigenvector centralities. Among the several algorithms used, the Power Method is one of the simplest iterative approaches. It relies on multiple vector-matrix multiplications (VMMs) and a normalization step to prevent divergent behaviours. Recently, efficiency of the memristor crossbars in solving VMMs have been demonstrated using fundamental laws of the circuit theory. In this work, we propose a circuit to accelerate the Power iteration algorithm including current-mode termination for the memristor crossbars and a normalization circuit. The normalization step together with the feedback loop of the complete circuit ensure stability and convergence of the dominant eigenvector. The system allows the observation of the evolution of the outputs. We implement a transistor level peripheral circuitry around the memristor crossbar and take non-idealities such as wire parasitics, source driver resistance and finite memristor precision into account. We compute the eigenvector centrality to demonstrate the performance of the proposed system. We compare our results to the ones coming from the conventional digital computers and observe significant energy savings while maintaining a competitive accuracy.

Weakly Connected Oscillatory Networks (WCONs) are bio-inspired models which exhibit associative memory properties and can be exploited for information processing. It has been shown that the nonlinear dynamics of WCONs can be reduced to equations for the phase variable if oscillators admit stable limit cycles with nearly identical periods. Moreover, if connections are symmetric, the phase deviation equation admits a gradient formulation establishing a one-to-one correspondence between phase equilibria, limit cycle of the WCON and minima of the system’s potential function. The overall objective of this work is to provide a simulated WCON based on memristive connections and Van der Pol oscillators that exploits the device mem-conductance programmability to implement a novel local supervised learning algorithm for gradient models: Equilibrium Propagation (EP). Simulations of the phase dynamics of the WCON system trained with EP show that the retrieval accuracy of the proposed novel design outperforms the current state-of-the-art performance obtained with the Hebbian learning.

Second order memristors are two terminal devices that present a conductance depending on two orders of variables, namely the geometric parameters and the internal temperature. They have shown to be able to mimic some specific features of neuron synapses, specifically Spike-Timing-Dependent-Plasticity (STDP), and consequently to be good candidates for neuromorphic computing. In particular, memristor crossbar structures appear to be suitable for implementing locally competitive algorithms and for tackling classification problems by exploiting temporal learning techniques. On the other hand, neuromorphic studies and experiments have revealed the existence of different kinds of plasticity and have shown the effect of calcium concentration on synaptic changes. Computational studies have investigated the behavior of spiking networks in the context of supervised, unsupervised, and reinforcement learning. In this paper, we first derive a simplified, almost analytical, model of a second-order memristor, only involving two variables, the mem-conductance, and the temperature, directly attributable to the synaptic efficacy and to the calcium concentration. Then we study in detail the response of a single memristive synapse to the most relevant plasticity models, including cycles of spike pairs, triplets, and quadruplets at different frequencies. Finally, we accurately characterize memristor spiking networks as discrete nonlinear dynamic systems, with mem-conductances as state variables and pre and postsynaptic spikes as inputs and outputs, respectively. The result shows that the model developed in this manuscript can explain and accurately reproduce a significant portion of observed synaptic behaviors, including those not captured by classical spike pair-based STDP models. Furthermore, under such an approach, the global dynamic behavior of memristor networks and the related learning mechanisms can be deeply analyzed by employing advanced nonlinear dynamic techniques.

Resistive devices such as memristors have attracted the researchers' attention as fundamental computing elements. The prime objective of this work is to provide a simulated analogue computing platform based on memristor devices and recurrent neural networks that exploits the memristor device conductance programmability to implement local learning algorithms. We present the application of two simple two-phase learning procedures for Dynamic Neural Networks used to solve a pattern reconstruction task. The first learning scheme is related to Energy-based models and the second generalizes this method to generic vector field dynamics, relaxing the requirement of an energy function. Experimental results show that both the two approach significantly outperforms conventional learning rules used for pattern reconstruction.

Problems involving discrete Markov Chains are solved mathematically using matrix methods. Recently, several research groups have demonstrated that matrix-vector multiplication can be performed analytically in a single time step with an electronic circuit that incorporates an open-loop memristor crossbar that is effectively a resistive random-access memory. Ielmini and co-workers have taken this a step further by demonstrating that linear algebraic systems can also be solved in a single time step using similar hardware with feedback. These two approaches can both be applied to Markov chains, in the first case using matrix-vector multiplication to compute successive updates to a discrete Markov process and in the second directly calculating the stationary distribution by solving a constrained eigenvector problem. We present circuit models for open-loop and feedback configurations, and perform detailed analyses that include memristor programming errors, thermal noise sources and element nonidealities in realistic circuit simulations to determine both the precision and accuracy of the analog solutions. We provide mathematical tools to formally describe the trade-offs in the circuit model between power consumption and the magnitude of errors. We compare the two approaches by analyzing Markov chains that lead to two different types of matrices, essentially random and ill-conditioned, and observe that ill-conditioned matrices suffer from significantly larger errors. We compare our analog results to those from digital computations and find a significant power efficiency advantage for the crossbar approach for similar precision results.