The intellectual property (IP) mapping problem is an NP-hard problem in network-on-chip (NoC) designs and is often solved by the genetic Algorithm. In the genetic algorithm (GA), new populations are generated by crossover and mutation operators. However, these operators consider neither the prior knowledge of the IP mapping problem nor the historical experience of the population evolution, easily causing the GA to converge prematurely to the local optima. To solve this problem, a learnable model-based GA (LMGA) is proposed, which introduces a learnable model and a hybridization scheme of the model and GA. 1) the learnable model is implemented by a novel neural network-based probability model for the IP mapping problem, i.e., the message passing attention network (MAN). Moreover, the learnable model is pretrained then updated by learning the features of high-fitness individuals among the population to predict a better probability distribution of the optimal solution in a specific IP mapping problem. 2) The scheme updates the population of certain generations of the GA by sampling the learnable model. Hence, the population evolution is guided by the learnable model to avoid premature convergence. Simulation results show that the MAN achieves a faster training speed and models the large-scale IP mapping problem better than the message passing neural network-pointer network (MPN) in the previous work. The LMGA saves an average of 5.68% and 5.23% in the communication energy and average network delay, respectively, than the state-of-the-art algorithm, i.e., the message passing neural network-pointer network-based genetic algorithm (MPN-GA).

The field-programmable gate array (FPGA)-based CNN hardware accelerator adopting single-computing-engine (CE) architecture or multi-CE architecture has attracted great attention in recent years. The actual throughput of the accelerator is also getting higher and higher but is still far below the theoretical throughput due to the inefficient computing resource mapping mechanism and data supply problem, and so on. To solve these problems, a novel composite hardware CNN accelerator architecture is proposed in this article. To perform the convolution layer (CL) efficiently, a novel multiCE architecture based on a row-level pipelined streaming strategy is proposed. For each CE, an optimized mapping mechanism is proposed to improve its computing resource utilization ratio and an efficient data system with continuous data supply is designed to avoid the idle state of the CE. Besides, to relieve the off-chip bandwidth stress, a weight data allocation strategy is proposed. To perform the fully connected layer (FCL), a single-CE architecture based on a batch-based computing method is proposed. Based on these design methods and strategies, visual geometry group network-16 (VGG-16) and ResNet-101 are both implemented on the XC7VX980T FPGA platform. The VGG-16 accelerator consumed 3395 multipliers and got the throughput of 1 TOPS at 150 MHz, that is, about 98.15% of the theoretical throughput ( 2 ×3395 ×150 MOPS). Similarly, the ResNet-101 accelerator achieved 600 GOPS at 100 MHz, about 96.12% of the theoretical throughput ( 2 ×3121 ×100 MOPS).

In network-on-chip (NoC) designs, the intellectual property (IP) mapping problem is a critical issue and is usually solved by heuristic searches. However, heuristic searches suffer from the problem of easily falling into the local optimum. To tackle this problem, this article proposes a reinforcement learning-based framework (RLF), which enhances the performance of heuristic searches through the neural network-based probability model. Within this framework, first, a neural network-based probability model for IP mapping is built and trained by reinforcement learning instead of supervised learning to overcome the difficulty of obtaining a high-quality labeled training set. Second, based on the pretrained probability model, the model-based heuristic uses the probability model to generate the initial population and then employs heuristic searches to find the optimal solution. Two model-based heuristics, i.e., the message passing neural network-pointer network-based genetic algorithm (MPN-GA) and the message passing neural network-pointer network-based PSMAP (MPN-PSMAP), are proposed as specific instances. Simulation results show that the MPN-GA reduces the communication cost by an average of 9.32% than the genetic algorithm (GA). The MPN-PSMAP achieves an average reduction in the communication cost of 8.37% than the PSMAP. Finally, two extensions are given as examples to show the good extensibility of this framework.

The IP core mapping optimization problem is an NP-hard problem in network-on-chip design. Because of the computational complexity of an IP core mapping, the MPNN-Ptr networks composed of the graph networks and the pointer networks are proposed to model the IP core mapping. The neural network IP core mapping model (NNMM) can effectively evaluate the probability of each mapping solution as the optimal solution to an IP core mapping optimization problem. Then, an IP core mapping algorithm, the neural mapping algorithm (NMA), is proposed. In this algorithm, the global search is realized by sampling the mapping solutions with a high probability evaluated by NNMM. The sampled candidate mapping solutions according to probability can effectively decrease the candidate mapping solution space, which can reduce invalid searches and avoid getting stuck at local minima. Then, the 2-opt algorithm is used as a local search to improve the quality of mapping further. Simulation results show that the MPNN-Ptr networks can effectively model the IP core mapping. Compared with the state-of-the-art mapping algorithms, NMA produces better solutions for both specific applications and random applications. NMA achieves a 7.90% communication cost reduction on average than the classic mapping algorithm: NMAP.