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Azin Heidarshenas

dblp:252/4610 · DBLP profile ↗
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5ranked-venue papers
2as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
High-performance computing · 60% Parallel and multicore computing · 22% Performance modeling and evaluation · 18%
Theoretical computer science
2 papers
Graph algorithms and graph theory · 100%
Databases, data mining, and information retrieval
1 paper
Machine learning and data management · 100%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
performance prediction
0.712023
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning · PPoPP 2023
High-performance computing
sparse linear algebra
0.712023
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning · PPoPP 2023
High-performance computing › sparse linear algebra › sparse matrix computation
SpMV
0.712023
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning · PPoPP 2023
Parallel and multicore computing
locality optimization
0.412020
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization · SC 2020
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication
0.412020
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization · SC 2020
High-performance computing › code optimization
vectorization
0.412020
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization · SC 2020
Parallel and multicore computing
task scheduling
0.412019
Understanding priority-based scheduling of graph algorithms on a shared-memory platform · SC 2019
Machine learning and data management › learned database components
learned performance model
0.212023
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning · PPoPP 2023
Graph algorithms and graph theory
graph processing
0.112019
Understanding priority-based scheduling of graph algorithms on a shared-memory platform · SC 2019

Methods — techniques the papers use, named apart from their topics

machine learning · 1.3locality-aware vectorization · 0.9CSR · 0.9concurrent priority scheduling · 0.8
YearPublicationVenuePosition
2023 WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning
abstract
Sparse Matrix-Vector Multiplication (SpMV) is an essential sparse kernel. Numerous methods have been developed to accelerate SpMV. However, no single method consistently gives the highest performance across a wide range of matrices. For this reason, a performance prediction model is needed to predict the best SpMV method for a given sparse matrix. Unfortunately, predicting SpMV's performance is challenging due to the diversity of factors that impact it.
Serif Yesil, Azin Heidarshenas, Adam Morrison 0001, Josep Torrellas
PPoPP2
2020 Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors
abstract
Many parallel algorithms in domains such as graph analytics and simulations rely on priority-based task scheduling. In such environments, the data structure of choice is a concurrent priority queue (PQ). Unfortunately, PQ algorithms exhibit an undesirable tradeoff. On one hand, strict PQs always dequeue the highest-priority task, and thus fail to scale because of contention at the head of the queue. On the other hand, relaxed PQs avoid contention by dequeuing tasks that are sometimes so far from the head that the resulting schedule misses the benefit of priority-based scheduling.
Azin Heidarshenas, Tanmay Gangwani, Serif Yesil, Adam Morrison 0001, Josep Torrellas
ICS1
2020 V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging
abstract
An iterative graph algorithm applies a vertex update operation to all vertices in a graph in every iteration. For large graphs, this computation is costly. However, in practice, not all the updates contribute equally to the end result and, in fact, an exact result may not be needed. In this work, we leverage these insights to speed-up iterative graph algorithms. We propose a mechanism to identify the less important vertices and omit computations for them.
Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos 0002, Sasa Misailovic, Adam Morrison 0001, Josep Torrellas
ICS1
2020 Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization
abstract
Graph analytics applications often target large-scale web and social networks, which are typically power-law graphs. Graph algorithms can often be recast as generalized Sparse Matrix-Vector multiplication (SpMV) operations, making SpMV optimization important for graph analytics. However, executing SpMV on large-scale power-law graphs results in highly irregular memory access patterns with poor cache utilization. Worse, we find that existing SpMV locality and vectorization optimizations are largely ineffective on modern out-of-order (OOO) processors-they are not faster (or only marginally so) than the standard Compressed Sparse Row (CSR) SpMV implementation. To improve performance for power-law graphs on modern OOO processors, we propose Locality-Aware Vectorization (LAV). LAV is a new approach that leverages a graph's power-law nature to extract locality and enable effective vectorization for SpMV-like memory access patterns. LAV splits the input matrix into a dense and a sparse portion. The dense portion is stored in a new representation, which is vectorization-friendly and exploits data locality. The sparse portion is processed using the standard CSR algorithm. We evaluate LAV with several graphs on an Intel Skylake-SP processor, and find that it is faster than CSR (and prior approaches) by an average of 1.5x. LAV reduces the number of DRAM accesses by 35% on average, with only a 3.3% memory overhead.
Serif Yesil, Azin Heidarshenas, Adam Morrison 0001, Josep Torrellas
SC2
2019 Understanding priority-based scheduling of graph algorithms on a shared-memory platform
abstract
Many task-based graph algorithms benefit from executing tasks according to some programmer-specified priority order. To support such algorithms, graph frameworks use Concurrent Priority Schedulers (CPSs), which attempt---but do not guarantee---to execute the tasks according to their priority order. While CPSs are critical to performance, there is insufficient insight on the relative strengths and weaknesses of the different CPS designs in the literature. Such insights would be valuable to design better CPSs for graph processing.
Serif Yesil, Azin Heidarshenas, Adam Morrison 0001, Josep Torrellas
SC2