The increasing susceptibility of aerospace integrated circuits (ICs) to single-event effects (SEEs) demands advanced radiation-hardening-by-design (RHBD) methodologies, especially for analog/mixed-signal circuits operating in extreme environments. While digital circuit hardening has seen extensive advancements, circuit-level radiation hardening techniques specifically targeting analog building blocks—such as high-speed current-mode logic (CML) latches used in frequency dividers—have received relatively less attention, largely due to the inherent trade-offs between radiation tolerance and high-speed performance. This work proposes a low-overhead RHBD strategy for CML latches in high-speed dividers, addressing single-event upsets (SEUs) through the integration of pMOS transistors at storage nodes to counteract charge collection induced by SEEs. The methodology is rigorously validated using calibrated double-exponential current source simulations, emulating SEEs. The hardened design demonstrates robust radiation tolerance across varied pMOS control signals and sizing parameters, with minimal sensitivity introduced at additional nodes. Postlayout simulations in sub-20 nm FinFET technology reveal a maximum operating frequency of 46 GHz, accompanied by ultralow implementation overheads: a 2% area penalty and 22% power increase. The strategy resolves critical trade-offs between radiation resilience and high-speed performance, offering a scalable solution for aerospace-grade circuits in radiation-intensive environments. This advancement underscores the viability of tailored RHBD approaches for analog/mixed-signal systems, enabling next-generation space electronics that harmonize reliability with cutting-edge functionality.