In harsh environments such as space, radiation and charged particles cause Single-Event Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single-Event Transients (SETs), but incur a minimum of$3\times $cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time To Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. In this paper, we propose In-Memory Error Code Correction Checking (IMECCC), a method to replace memory scrubbing and improve FPGA configuration memory protection in high radiation environments. Our method allows asynchronous SEU detection, and replaces the scrubbing’s variable time to detect with a fixed TTD. We show that IMECCC reduces FPGA’s TTD by at least 116,$000\times $on average, with an area increase of$1.56\times $, using a test architecture resembling a Xilinx Virtex 5 QV at a 60MHz scrubbing frequency.

In harsh environments, such as space, radiation, and charged particles cause single-event effects (SEEs), faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy (TMR), are very effective against single-event transients (SETs) but incur a minimum of$3\times $cost in the area. Single-event upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process going through every memory word, looking for errors to repair. Scrubbing involves a nonnegligible amount of time before an error is detected, during which other events can occur and compromise the system. Field-programmable gate arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design sustainability in harsh conditions. In this article, we propose an alternative mitigation method based on sensor integration and FPGA architecture modification, called smart-redundancy with in-memory error correction code checking (SRIMECCC). The sensors allow asynchronous SEU detection, reducing the time to detect by 57$250\times $on average and enabling local reconfiguration. Our method includes built-in dual redundancy that reduces the power consumption by 87% on average, benefiting embedded systems. SRIMECCC is also an area-efficient technique that saves 28% of total effective area compared to TMRed designs implemented in FPGAs.

Field Programmable Gate Arrays (FPGAs) reconfigurability is a key asset for many critical applications. State- of-the-art Radiation-Hardening (Rad-Hard) methods for FPGAs consist of triplicating the logic, reinforcing the memories, and bitstream scrubbing with partial reconfiguration. These methods involve a 3× reduction of Maximal Design Capacity (MDC) and an average Time-In-Error (TIE) proportional to design sizes. In this paper, we propose an alternative: Smart-Redundancy (SR), a new method based on the detection of possible events via process and hardware modifications. Thanks to integrated particle sensors, only dual redundancy is required. Results show up to 33.33% improvement in MDC over actual Rad-Hard methods, and an average TIE decrease of at least 10,000× compared to bitstream's scrubbing, at a cost of 41.08% in area using a commercial 40nm technology node.

Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. In this paper, we introduce OpenFPGA, an opensource framework that enables rapid prototyping of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. OpenFPGA also includes a general-purpose Verilog-to-Bitstream generator for any FPGA described by the XML language. We demonstrate the capability of this automatic design flow with a Stratix IV-like FPGA architecture using a commercial 40nm technology node, and perform a detailed comparison to its academic and commercial counterparts. Compared to the current state-of-art academic results, our FPGA fabric reduces the area by 1:75 and the delay by 3 on average. In addition, OpenFPGA significantly reduces the gap between semi-custom designed FPGAs and fully-optimized commercial products with a penalty of only 60% in area and 30% in delay, respectively.