Demo Data from EDBT 2026 / reviewers in the wild / expert
Roland N. Green
dblp:252/8066
· DBLP profile ↗
4ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 since 2021Software engineering, systems software and programming languages · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
GPUs and heterogeneous computing · 50% Performance modeling and evaluation · 50% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
simulation |
0.5 | 1 | 2021 | Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads · MICRO 2021 |
Performance modeling and evaluation
workload characterization |
0.5 | 1 | 2021 | Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads · MICRO 2021 |
GPUs and heterogeneous computing
GPU microarchitecture |
0.4 | 1 | 2020 | Dimensionality-Aware Redundant SIMT Instruction Elimination · ASPLOS 2020 |
GPUs and heterogeneous computing › GPU microarchitecture
SIMT execution |
0.4 | 1 | 2020 | Dimensionality-Aware Redundant SIMT Instruction Elimination · ASPLOS 2020 |
GPUs and heterogeneous computing
GPU architecture |
0.1 | 1 | 2021 | Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads · MICRO 2021 |
Compilers and program optimization › accelerator compilation
GPU compiler optimization |
0.1 | 1 | 2020 | Dimensionality-Aware Redundant SIMT Instruction Elimination · ASPLOS 2020 |
Methods — techniques the papers use, named apart from their topics
static compiler marking · 0.9non-speculative instruction skipping · 0.9kernel launch-time information · 0.9principal kernel analysis · 0.5cycle-level simulation · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU WorkloadsabstractSimulating all threads in a scaled GPU workload results in prohibitive simulation cost. Cycle-level simulation is orders of magnitude slower than native silicon, the only solution is to reduce the amount of work simulated while accurately representing the program. Cesar Avalos Baddouh, Mahmoud Khairy, Roland N. Green, Mathias Payer, Timothy G. Rogers |
MICRO | 3 |
| 2020 | Dimensionality-Aware Redundant SIMT Instruction EliminationabstractIn massively multithreaded architectures, redundantly executing the same instruction with the same operands in different threads is a significant source of inefficiency. This paper introduces Dimensionality-Aware Redundant SIMT Instruction Elimination (DARSIE), a non-speculative instruction skipping mechanism to reduce redundant operations in GPUs. DARSIE uses static markings from the compiler and information obtained at kernel launch time to skip redundant instructions before they are fetched, keeping them out of the pipeline. DARSIE exploits a new observation that there is significant redundancy across warp instructions in multi-dimensional threadblocks. Tsung Tai Yeh, Roland N. Green, Timothy G. Rogers |
ASPLOS | 2 |
| 2019 | POSTER: Quantifying the Direct Overhead of Virtual Function Calls on Massively Parallel ArchitecturesabstractProgrammable accelerators aim to provide the flexibility of traditional CPUs, with greatly improved performance and energy-efficiency. Arguably, the greatest impediment to the widespread adoption of programmable accelerators, like GPUs, is the software engineering overhead involved in getting the code to execute correctly. To help combat this issue, GPGPU computing has matured from its origins as a collection of graphics API hacks to include advanced programming features, including object-oriented programming. This level of support, in combination with a shared virtual memory space between the CPU and GPU, make it possible for rich object-oriented frameworks to execute on GPUs with little porting effort. However, executing this type of flexible code on a massively parallel accelerator introduces overhead that has not been well studied. In this poster, we analyze the direct overhead of virtual function calls on contemporary GPUs. Using the latest GPU architectures and compilers, this poster performs the analysis of how virtual function calls are implemented on GPUs. We quantify the direct overhead incurred from contemporary implementations and show that the massively multithreaded nature of GPUs creates deficiencies and opportunities not found in CPU implementations of virtual function calls. Mengchi Zhang, Roland N. Green, Timothy G. Rogers |
PACT | 2 |
| 2018 | Characterizing the Runtime Effects of Object-Oriented Workloads on GPUsabstractModern GPGPU programming extensions like OpenCL and CUDA have supported object-oriented workloads on GPUs for several generations. However, no analysis of object-oriented workloads running on massively parallel accelerators has been investigated. This extended abstract presents a performance analysis of object-oriented workloads on a PASCAL Titan X GPU. Our characterization demonstrates that GPUs have different performance trade-offs when running object-oriented code than traditional CPUs. Where CPUs are sensitive to the misprediction of indirect branches that result from virtual function calls, GPUs are more sensitive to the additional memory system pressure that comes from loading pointers and virtual function table entries. Mengchi Zhang, Roland N. Green, Timothy G. Rogers |
ISPASS | 2 |