Sparse matrix-vector multiplication ($S$pMV) is pivotal in many scientific computing and engineering applications. Considering the memory-intensive nature and irregular data access patterns inherent in SpMV, its acceleration is typically bounded by the limited bandwidth. Multiple memory channels of the emerging high bandwidth memory (HBM) provide exceptional bandwidth, offering a great opportunity to boost the performance of SpMV. However, ensuring high bandwidth utilization with low memory access conflicts is still non-trivial. In this paper, we present Cuper, a high-performance SpMV accelerator on HBM-equipped FPGAs. Through customizing the dataflow to be HBM-compatible with the proposed sparse storage format, the bandwidth utilization can be sufficiently enhanced. Furthermore, a two-step reordering algorithm and perceptual decoder-centric hardware architecture are designed to greatly mitigate read-after-write (RAW) conflicts, enhance the vector reusability and on-chip memory utilization. The evaluation of 12 large matrices shows that Cuper's geomean throughput outperforms the four latest SpMV accelerators HiSparse, GraphLily, Sextans, and Serpens, by 3.28×, 1.99×, 1.75×, and 1.44×, respectively. Furthermore, the geomean bandwidth efficiency shows 3.28×, 2.20×, 2.82×, and 1.31x improvements, while the geomean energy efficiency has 3.59×, 2.08×, 2.21×, and 1.44× optimizations, respectively. Cuper also demonstrates 2.51× throughput and 7.97× energy efficiency of improvement over the K80 GPU on 2,757 SuiteSparse matrices.

Solving systems of linear equations is a fundamental problem in scientific computing, which has been extensively researched for decades. One of the most well-known solvers is Algebraic Multigrid (AMG), which is widely used in high performance computing due to its good scalability. But currently accelerating AMG relies on the traditional von Neumann architecture of storage and computation separation, which leads to a large data transmission overhead. In this work, we propose a ReRAM-based processing-in-memory (PIM) architecture named AmgR, which overcomes the limitations of the traditional von Neumann architecture for AMG acceleration.However, accelerating AMG on ReRAM is non-trivial, because (1) AMG has many computing kernels of various types; (2) there are irregular operations that cannot be directly performed using matrix-vector multiplication suitable for ReRAM, i.e., aggregation operation; (3) ReRAM has poor write endurance, and a lot of data during AMG acceleration needs to be rewritten into ReRAM, resulting in high write cost. To address these issues, firstly, we propose a flexible architecture, which can realize each kernel of AMG and is reused by many kernels to improve resource utilization. Secondly, we propose a dedicated unit to realize the aggregation operation. Finally, we present a new mapping strategy to greatly reduce the number of data handling and writes. The experimental results show that the performance of AmgR is improved by an average of one and two orders of magnitude compared to HYPRE on the CPU and AmgX on the GPU, respectively, while the energy consumption is reduced by an average of two and three orders of magnitude.

With the increasing complexity of integrated circuits, it is becoming cumulatively challenging to solve the entire large-scale nonlinear algebraic system in DC analysis within reasonable simulation time and without accuracy lost. For this reason, we present an efficient parallel arclength approach called PALBBD to solve DC problems for large capacity and full accuracy in this paper. We process the m+1 dimensions equation of the Newton-Raphson (NR) iteration in an alternative way, which maintains the Jacobian matrix structure. Besides, we exploit the bordered block diagonal (BBD) form to save the matrix for parallel computing. Moreover, we check the convergence of each sub-partition and bypass the calculations of converged ones to reduce the amount of unnecessary computations during the iteration. In order to ensure the accuracy, we use a correction equation to replace the Schur complement updating for the bypassed sub-partitions. The proposed PALBBD is implemented and integrated to the SPICE simulator and verified by 72 real-world circuits. It outperforms the conventional serial arclength method with up to 73.93X speedup and 45% bypass ratio.

Due to the different shapes of buildings and the cross-distribution with various surface types around them, it is difficult to extract buildings in high precision using traditional classification methods. The deep learning method based on neural network can mine useful information of remote sensing image in depth and improve the accuracy of building recognition. However, the application of neural network in building extraction is limited because of the large number of parameters involved and the large demand for training samples. In order to improve the accuracy of building extraction in remote sensing images by using deep learning method, identity skip connection is inserted into U-net network for samples training, which effectively reduces the number of parameters, significantly reduces the size of the model, and avoids the gradient explosion caused by the deepening of the number of layers, and obviously improves the accuracy of segmentation. By comparing the results of different layers, it is shown that with the deepening of layers, the accuracy increases.