This paper proposes a Vref-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a Vcm-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (Vref) based on the sign of the mismatch error. Consequently, the adjusted Vrefcompensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm2area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.

The linearity of the digital-to-analog converter (DAC) is a key bottleneck for high-resolution Sigma-Delta modulators that use multi-level quantizers. To address the DAC non-linearities caused by element mismatches and achieve a high signal-to-noise-and-distortion ratio (SNDR), this work exploits intrinsically linear capacitive DACs to improve the design of a high-resolution Sigma-Delta modulator with 4th-order, discrete-time architecture realized as a Cascade of Integrators with Feed Back (CIFB), and 3-level/5-level quantizers. The error due to capacitive element mismatch is mitigated by using an extra reference voltage and reconfiguring DAC topologies so that distortions brought by capacitor mismatches are largely reduced. We demonstrate in simulation results that a 128.9 dB modulator SNDR can be obtained in the presence of up to 1% DAC capacitance mismatch combined with 2% reference voltage variation, achieving 60 dB SNDR improvement compared with a design with a conventional DAC structure.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.