High-speed cross-chip interconnects and packaging are critical for the overall performance of modern heterogeneous integrated computing systems. Recent studies have developed automatic stack-up design optimization methods for high-density interconnect (HDI) printed circuit board (PCB). However, few have considered the impact of manufacturing variation and the resulting yield issue in high-volume manufacturing (HVM). In this paper, we propose a novel framework for automatic stack-up design, optimizing the interconnect performance with a given yield requirement. The proposed framework utilizes the smooth and gradient-available machine learning surrogate model, employing a first-order Taylor expansion to approximate the output performance distribution. Experimental results demonstrate that our method effectively boosts the yield rate compared to the existing stack-up optimization framework. In addition, the proposed yield-aware algorithm shows an average of 49.96% efficiency improvement in yield-aware figure of merits compared to the state-of-the-art input noise-aware Bayesian optimization algorithm for high yield targets.

The future of computing requires heterogeneous integration, including the recent adoption of chiplet methodology, where high-speed cross-chip interconnects and packaging are critical for the overall system performance. As an example of advanced packaging, a high-density interconnect (HDI) printed circuit board (PCB) has been widely used in complex electronics ranging from cell phones to computing servers. A modern HDI PCB may have over 20 layers, each with its unique material properties and geometrical dimensions, i.e., stack-up, to meet various design constraints and performance requirements. Stack-up design is usually done manually in the industry, where experienced designers may devote many hours adjusting the physical dimensions and materials in order to meet the desired specifications. This process, however, is time-consuming, tedious, and suboptimal, largely depending on the designer’s expertise. In this article, we propose to automate the stack-up design with a new framework, ISOP+, using machine learning (ML) for inverse stack-up optimization for advanced package design with adaptive weight adjustment and multilevel optimization. Given a target design specification, ISOP+ automatically searches for ideal stack-up design parameters while optimizing performance. A novel ML-assisted hyperparameter optimization method is developed to make the search efficient and reliable. Experimental results demonstrate that ISOP+ is better in figure-of-merit (FoM) than conventional simulated annealing and Bayesian optimization algorithms, with all our design targets met with a shorter runtime. We also compare our fully automated ISOP+ with expert designers in the industry and achieve very promising results, with orders of magnitude reduction of turn-around time.

Future computing calls for heterogeneous integration, e.g., the recent adoption of the chiplet methodology. However, high-speed cross-chip interconnects and packaging shall be critical for the overall system performance. As an example of advanced packaging, a high-density interconnect (HDI) printed circuit board (PCB) has been widely used in complex electronics from cell phones to computing servers. A modern HDI PCB may have over 20 layers, each with its unique material properties and geometrical dimensions, i.e., stack-up, to meet various design constraints and performance optimizations. However, stack-up design is usually done manually in the industry, where experienced designers may devote many hours to adjusting the physical dimensions and materials to meet the desired specifications. This process, however, is time-consuming, tedious, and sub-optimal, largely depending on the designer's expertise. In this paper, we propose to automate the stack-up design with a new framework, ISOP, using machine learning for inverse stack-up optimization for advanced package design. Given a target design specification, ISOP automatically searches for ideal stack-up design parameters while optimizing performance. We develop a novel machine learning-assisted hyper-parameter optimization method to make the search efficient and reliable. Experimental results demonstrate that ISOP is better in figure-of-merit (FoM) than conventional simulated annealing and Bayesian optimization algorithms, with all our design targets met with a shorter runtime. We also compare our fully-automated ISOP with expert designers in the industry and achieve very promising results, with orders of magnitude reduction of turn-around time.

A key problem when modeling signal integrity for passive filters and interconnects in IC packages is the need for multiple S-parameter measurements within a desired frequency band to obtain adequate resolution. These samples are often computationally expensive to obtain using electromagnetic (EM) field solvers. Therefore, a common approach is to select a small subset of the necessary samples and use an appropriate fitting mechanism to recreate a densely-sampled broadband representation. We present the first deep generative model-based approach to fit S-parameters from EM solvers using one-dimensional Deep Image Prior (DIP). DIP is a technique that optimizes the weights of a randomly-initialized convolutional neural network to fit a signal from noisy or under-determined measurements. We design a custom architecture and propose a novel regularization inspired by smoothing splines that penalizes discontinuous jumps. We experimentally compare DIP to publicly available and proprietary industrial implementations of Vector Fitting (VF), the industry-standard tool for fitting S-parameters. Relative to publicly available implementations of VF, our method shows superior performance on nearly all test examples using only 5 – 15% of the frequency samples. Our method is also competitive to proprietary VF tools and often outperforms them for challenging input instances.