Shivam Chaturvedi

dblp:254/4227 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2024
0000-0003-1533-0857ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021
YearPublicationVenuePosition
2024 Mitigation of negative impedance instabilities in a three phase interleaved boost converter feeding constant power load
abstract
An interleaved converter consists of multiple phases operating out of phase with the well known benefits of reduced input output current and ripples, improved efficiency and better thermal performance. When the interleaved converter is connected to a constant power load, its negative incremental impedance characteristics leads to instability. This leads to an increased oscillation in the DC link voltage and the source current which is interfaced with the interleaved converter. In this manuscript, a robust control consisting of the sliding mode control is proposed to damp the oscillations due to CPL and maintain the DC link voltage and source current within the permissible desired limits. The proposed sliding manifold consists of the power error terms and a voltage error term. The proposed control performance is validated through simulation and experimental results on a 500W three phase interleaved boost feeding a buck converter fed resistive load setup.
Shivam Chaturvedi, Shahid Aziz Khan, Duc Dung Le 0003, Mengqi Wang, Wencong Su
IECON1
2024 An RMRAC-based Adaptive and Robust Control for a Multi-Winding Flyback Converter in OBC Application
Shahid Aziz Khan, Guilherme Vieira Hollweg, Mengqi Wang, Wencong Su, Shivam Chaturvedi, Duc Dung Le 0003, Mahdi Ghavaminejad
IECON5
2024 A Capacitor Voltage-Balancing Method for Modular Multilevel Converter with Three-level SMs in Variable-speed Drives
abstract
The three-level submodule (3L SM) has emerged as a viable alternative to the conventional half-bridge submodule in modular multilevel converters (MMC), primarily due to its reduced footprint. Despite this, there has been no in-depth exploration of MMC topologies utilizing 3L SMs, particularly in the context of motor drive applications. The 3L SM features two capacitors, and the MMC relies on a cascade connection of multiple 3L SMs per phase, necessitating voltage-balancing control for these capacitors. This paper introduces a voltage-balancing control strategy for multiple capacitors, incorporating high-frequency voltage and circulating current injections to ensure optimal performance in low-speed motor drive operations. The voltage commands are normalized and compared with phase-shifted carrier (PSC) PWM triangular waveforms to generate gating signals. The proposed voltage-balancing control method has been validated through a 4160-V/1-MW simulation model using a hardware-in-the-loop (HIL) system.
Duc Dung Le 0003, Shivam Chaturvedi, Shahid Aziz Khan, Mahdi Ghavaminejad, Mengqi Wang, Wencong Su
IECON2