Dynamic voltage and frequency scaling (DVFS) is commonly used for the balance of performance and power of mobile processors. Conventional DVFS regulators take the processor cores with the same power and performance weight showing their inability in the regulation of heterogeneous processors. This paper proposes a core-aware frequency-power evaluation scheme that utilizes a multilayer perceptron (MLP) to assess the efficacy of DVFS regulation actions. Additionally, a ResNet-based DVFS regulator, trained with the assistance of the MLP, is developed for heterogeneous multi-core processors. Evaluated on Xiaomi 13 Pro powered by a Qualcomm Snapdragon 8 Gen 2, the proposed DVFS approach achieves an up to ×1.47 improvement in FPS Performance Per Watt (FPPW) compared with the Qualcomm's default DVFS governor in video recording scenario.

Reinforcement learning (RL) based dynamic voltage and frequency scaling (DVFS) is an effective approach to balance performance and power consumption for video rendering applications. To approximate the “God’s eye view” regulation, the CPU-GPU should be fine-grained regulated and the SoC have to be fully observed by a RL-based DVFS governor. Fine-grained regulation with traditional value-based RL governor suffers action space explosion and it is impossible to have a fully observable SoC. To address these two issues, a governor based on deep recurrent deterministic gradient (DRDPG) governor is proposed. The governor is based on Deterministic Policy Gradient (DDPG) algorithm with embedded recurrent neural network (RNN). The DDPG algorithm guarantees fine-grained power regulation without action space explosion and the RNN-FC network topology mitigates the partial observability issue. Evaluated on the Nvidia Jetson NX platform, the proposed DRDPG governor achieves over 19% better regulation efficiency compared with Linux default governors and shows superior regulation efficiency to other RL-based state-of-the-arts. Implemented in a 55-nm CMOS process, the proposed governor draws merely 2.16-mA from a 1.2-V supply at 1-MHz clock occupying a silicon area of 0.075mm$^2$.

This paper presents the analysis and behavioral modeling of two high-order DAC linearity enhancement techniques and constructs a third-order noise-shaping (NS) SAR ADC with full-bit high-order mismatch-shaped capacitor DAC(CDAC) to verify the performance. The CDAC is divided into an MSB segment and two LSB segments, where a third-order VMS and a second-order MES are utilized to deal with the capacitance mismatch respectively. With the enhancement of the behavioral model, optimizations focused on the mismatch transfer function (MTF) and segment length of MSB and LSB are made. The simulation results of obtained system achieve 113.25dB SNDR and 18.52 ENOB when 1% CDAC mismatch is introduced.

Malicious manipulation of very large-scale integration physical-layout design is a serious problem in modern integrated circuit design. The physical-layout design database requires a highly compressed secured storage medium. In this article, we propose a secured compressive asymmetrical convolutional auto-encoder (ACAE) machine learning framework, CompressKey, which performs layout compression and encryption simultaneously. It utilizes geometric features to eliminate redundancies in layout patterns. We propose a “Divide and Merge” technique to partition each layer into smaller sizes of unique patterns to address the inconsistency of layout pattern complexity. We also propose “Matrix Expansion” and “Matrix Reduction” techniques on the matrix-based pattern to achieve secured “near lossless” compression on the layouts. We have evaluated CompressKey on 14/28/32 nm open-source ICCAD contest databases and achieved a secured compression ratio of 4.54 with encryption features outperforming$1.22\times $–$1.59\times $compared to the state-of-the-art techniques.