A change from a non-return-to-zero (NRZ) signaling to a four-level pulse amplitude modulation (PAM-4) signaling causes various challenges in clock and data recovery (CDR) designs as well as analog-front-end (AFE) designs. A PAM-4 CDR with a 2x-oversampling phase detector (PD) has an issue of increased pattern-dependent jitter due to asymmetric transitions. This work investigates a similar problem in a baud-rate CDR by analyzing the PD characteristics. In the PAM-4 baud-rate sampling, the transitions are classified into two types: full-swing transitions and non-full-swing transitions. Since utilizing the non-full-swing transitions can affect the jitter tracking ability, careful consideration of decisions using these transitions is necessary to optimize the jitter performance. To address this issue, we propose an asymmetric-weighted PD that minimizes pattern-dependent jitter and maximizes a transition density by utilizing both the full-swing transitions and the non-full-swing transitions. Using a pseudo-linear analysis, the proposed PD achieves improved jitter performance compared to the conventional PD. Fabricated in 28-nm CMOS process, a prototype PAM-4 receiver with the proposed CDR is demonstrated at 40 Gb/s. The CDR achieves a bit error rate (BER) less than 10$^{-9}$and an energy efficiency of 1.65 pJ/b.

This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a$\beta $detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the$\beta $detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm$^{2}$. The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than 10$^{-12}$and energy efficiency of 2.52 pJ/b.

This paper presents a 14–28 G/bs reference-less Baud-rate clock and data recovery (CDR) with a stochastic phase and frequency detector (PFD). To achieve phase and frequency detection, optimum weight is determined through the histogram-based correlation of various data patterns. Many data patterns within a wide frequency range are utilized to demonstrate robust operation. The reference-less Baud-rate CDR is implemented utilizing data samples and phase error samples obtained from the integrator. The proposed CDR is designed to achieve a data rate of up to 28 Gb/s employing a continuous-time linear equalizer (CTLE) under a 4.7-dB data loss channel at Nyquist frequency. Fabricated in 28-nm CMOS technology, the proposed CDR achieves a bit error rate (BER)−12and energy efficiency of 1.06 pJ/b.