This paper presents a novel charge-controlled, resistorless memristor emulator configuration based on current-mode building blocks, specifically an Operational Transconductance Amplifier (OTA), an Operational Transresistance Amplifier (OTRA), and a grounded MOS capacitor. The proposed design focuses exclusively on grounded incremental and decremental memristor configurations. It eliminates the need for resistors, analog multipliers, or ADC/DAC components, simplifying the architecture and enhancing its integration potential. The emulator's memristance is electronically tunable through the bias voltage of the OTRA and is accurately modeled as a function of the input signal flux. Simulation results, using Cadence Virtuoso with 0.18 µm CMOS technology, confirm stable pinched hysteresis behavior up to 20 MHz. The design exhibits robust performance under various conditions, including temperature variations, process corners, and a range of capacitor values. The proposed configuration demonstrates low power consumption, measured at just 1.019 mW. Its non-volatile characteristics are validated through pulsed signal testing, confirming its suitability for memory-retaining applications. Also, experimental verification using commercially available ICs supports the simulation outcomes. This grounded memristor emulator offers a practical, energy-efficient, and scalable solution for integration into analog and neuromorphic systems.

The design of the memristor emulator, which has found widespread of applications in analog computation, neuromorphic and biological systems, communications, etc., is much sought for. In this article, a resistorless electronically tunable grounded and floating memristor emulator by employing current-mode (CM) building blocks: operational transconductance amplifier (OTA) and voltage differencing buffered amplifier (VDBA) has been proposed. The proposed emulators can be configured as incremental and decremental operations. The robustness of the proposed emulator has been verified by performing various analyses: nonideal interpretations, process corner variations, temperature fluctuations, and nonvolatility behavior. The layout has been performed, and the theoretical fingerprint characteristics have been simulated and observed using 180-nm CMOS process parameters in the Cadence environment. The pinched hysteresis loop of the proposed memristor emulator maintains up to 5 MHz. The proposed memristor emulator uses less number of circuit components, but it maintains performance in terms of speed and operating range of frequency. Binary frequency shift keying (BFSK) has been performed using the proposed memristor to validate its functionality in the application. This memristor emulator with superior performance can be integrated into the communication system, analog computation, neuromorphic and biological systems, etc.

This article describes a realization of higher-order Inverse Band Pass Filter (SO-IBPF) configuration for low-power applications based on Current Differencing Buffered Amplifier (CDBA) as active elements and a few passive components. The proposed structure is proficient to operate with 0.6V supply voltage, 0.45V bias voltage and dissipates 0.918mW power. To justify the practicability of the proposed design, frequency and phase response outputs are produced through PSPICE simulation using 0.18μm TSMC CMOS process parameters. The other performance investigations such as sensitivity, non-ideality, input-output noise analysis, temperature variations, Monte-Carlo analysis and percentage of total harmonic distortion (%THD) are also examined. Moreover, the proposed configuration is experimentally tested using commercially available IC AD844AN to verify the theoretical propositions and simulation results. The layout of the proposed structure is also realized with Analog Design Environment tool (ADE) of Cadence/ spectre environment.

An application-based memristor prototype by employing only a single Voltage Difference Transconductance Amplifier (VDTA) as an active device and one grounded MOS-capacitor is reported in this research article. The transient analysis, pinched hysteresis loop for various frequencies along with serial and parallel combinations of the memristor are also examined. This grounded memristor design can suitably operate up-to MHz ranges. As an application of the stated memristor prototype, demodulation of grounded memristor-based Binary Frequency Shift Keying (BFSK), Amplitude Demodulation and a realization of Schmitt trigger configurations are shown. Moreover, the layout of this memristor is performed which occupies an effective area of 1432μm2. The simulation and layout of the entire design are implemented using Analog Design Environment (ADE) tool of the Cadence Virtuoso.

Three novel configurations of second order inverse band reject filters (IBRFs) are proposed in this work by using a single operational transresistance amplifier (OTRA). The working of the proposed inverse filters are verified in simulation by implementing 180 nm CMOS model of OTRA in SPICE and also in hardware with AD844AN IC. Theoretical frequency response characteristics of all the three proposed configurations match very well with the simulated characteristics. Layout of the proposed configuration has been implemented using Analog Design Environment (ADE) tool of cadence virtuoso to study the feasibility of operation. Monte Carlo analysis has also been performed to study the effect of variation in passive components on the performance of the circuits. Sensitivity analysis has been studied.