Demo Data from EDBT 2026 / reviewers in the wild / expert
Kingshuk Majumder
dblp:255/6001
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Reconfigurable computing and FPGAs · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA accelerator |
0.7 | 1 | 2023 | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description · ASPLOS (4) 2023 |
Electronic design automation › high-level synthesis
hardware compilation |
0.7 | 1 | 2023 | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description · ASPLOS (4) 2023 |
Electronic design automation › design representation
intermediate representation |
0.7 | 1 | 2023 | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description · ASPLOS (4) 2023 |
Compilers and program optimization › compiler infrastructure
MLIR |
0.2 | 1 | 2023 | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description · ASPLOS (4) 2023 |
Methods — techniques the papers use, named apart from their topics
compiler infrastructure · 1.3MLIR · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | HIR: An MLIR-based Intermediate Representation for Hardware Accelerator DescriptionabstractThe emergence of machine learning, image and audio processing on edge devices has motivated research towards power-efficient custom hardware accelerators. Though FPGAs are an ideal target for custom accelerators, the difficulty of hardware design and the lack of vendor agnostic, standardized hardware compilation infrastructure has hindered their adoption. Kingshuk Majumder, Uday Bondhugula |
ASPLOS (4) | 1 |