Hardware Trojans (HTs) are malicious circuits that can be inserted into integrated circuits (ICs) during the design, manufacturing, or packaging phases. HTs can cause a variety of security and safety problems, such as data theft, denial-of-service attacks, and physical damage. A scalable reference-free framework is introduced in this paper for netwise gate-level detection of existing and unknown HTs. The proposed framework consists of embedding-based automated netlist graph analysis and a supervised convolution-based classification of the individual IC net embeddings. A novel convolution algorithm for learning embedded IC graphs has been developed to overcome fundamental scalability limitation of existing graph convolutional neural networks. The performance of the proposed framework is experimentally demonstrated based on the TrustHub TRIT-TC benchmark suite, yielding a high recall of 96% and a precision of 86% for the netwise detection. The individual HT-compromised nets are highlighted within less than 0.1 seconds in >17,000-gate ICs. The proposed framework provides a scalable way to detect existing and unknown HTs without relying on HT-free reference ICs and can be effectively applied to large complex modern ICs. The unique combination of these characteristics makes the proposed framework more practical for real-world hardware cybersecurity applications as compared with prior art.

A multiterminal obstacle-avoiding pathfinding approach is proposed. The approach is inspired by deep image learning. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a pathfinding task as a graphical bitmap and consequently map a pathfinding task onto a pathfinding solution represented by another bitmap. To enable the proposed cGAN pathfinding, a methodology for generating synthetic dataset is also proposed. The cGAN model is implemented in Python/Keras, trained on synthetically generated data, evaluated on practical VLSI benchmarks, and compared with state-of-the-art. Due to effective parallelization on GPU hardware, the proposed approach yields a state-of-the-art-like wirelength and a better runtime and throughput for moderately complex pathfinding tasks. However, the runtime and throughput with the proposed approach remain constant with an increasing task complexity, promising orders of magnitude improvement over state-of-the-art in complex pathfinding tasks. The cGAN pathfinder can be exploited in numerous high throughput applications, such as, navigation, tracking, and routing in complex VLSI systems. The last is of particular interest to this work.

While financially preferable, pre-silicon hardware Trojan (HT) detection remains a primary security challenge in modern integrated circuits (ICs) In this paper, a pre-silicon framework is developed for identifying rarely triggered nets (including those of HTs) Unsupervised knowledge graph embedding is utilized to transform the conditional triggering probability of IC nets into the Euclidean distance between the nets’ embeddings The proposed approach is not limited by HT types/IC sizes and is reference-free The framework is evaluated with TrustHub benchmarks, fully supporting the theoretical results HTs are identified in the center of the embeddings’ cloud, reducing the HT search space by over 10X.

Obstacle-avoiding multiterminal net routing approach is proposed. The approach is inspired by deep learning image processing. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a routing task as a graphical bitmap and consequently map it to an optimal routing solution represented by another bitmap. The system is implemented in Python/Keras, trained on synthetically generated data, evaluated on typical high-resolution benchmarks, and compared with state-of-the-art traditional deterministic and deep learning solutions. The proposed system yields between 10.75x and 83.33x speedup over the traditional router without wirelength overhead due to effective parallelization on GPU hardware.

A global router is proposed that learns from routed circuits and autonomously routes unseen layouts. The uniqueness of this approach is in redefining the global routing as a classical image-to-image processing problem. The imaging problem is efficiently solved with a deep learning system, comprising a variational autoencoder and custom loss function. This fundamentally new routing method provides a natural way for global routing parallelization. The deep router is designed, trained, and tested on an unseen 64×64 ISPD'98 benchmark circuit. The test results yield 3.2% decrease in routability and over 5X speedup in runtime as compared with the state-of-the-art FastRoute router.

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems.