EDBT 2026 Demo / reviewers in the wild / expert
Maitreyi Ashok
dblp:255/6988
· DBLP profile ↗
6ranked-venue papers
3as first author
5since 2021 · last 2025
0000-0002-7621-2224ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021Artificial intelligence and machine learning · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data InputabstractWe present an ML-driven framework for predicting circuit performance metrics, bridging the gap between schematic and layout simulations, multi-process corner analysis, and measured silicon data. We focus on 14nm and 5nm FinFET-based ring oscillators, collecting data across varying supply voltages, temperatures, and process corners. Using three baseline ML models—XGBoost, Random Forest, and a Neural Network—we simulate real-world design scenarios where parameter fine-tuning may not always be feasible. Key tasks include predicting layout performance from schematic data, performance prediction across process corners, and predicting measured chip performance via transfer learning. Our results show that these models can achieve less than 5% mean absolute percentage error (MAPE) for power and frequency prediction while reducing required simulations by more than 2×. In migrating from 14nm to 5nm, XGBoost and Neural Network achieve high accuracy (>0.99 R2) using just 10% of 5nm simulations. This framework offers a promising approach to accelerating circuit design across technology nodes, reducing simulation costs while maintaining accuracy in predicting performance. Dimple Vijay Kochar, Maitreyi Ashok, John Cohn, Anantha P. Chandrakasan, Xin Zhang 0025 |
ISCAS | 2 |
| 2025 | Protecting the Mixed-Signal Domain: Secure ADCs for Internet of Things Devices
Maitreyi Ashok, Ruicong Chen, Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee |
Proc. IEEE | 1 |
| 2025 | Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement With Minimal Data InputabstractWe present an ML-driven framework for predicting circuit performance metrics, bridging the gap between schematic and layout simulations, multi-process corner analysis, and measured silicon data. We demonstrate this using 14nm and 5nm FinFET-based ring oscillators, by collecting data across varying supply voltages, temperatures, and process corners. Using three baseline ML models—XGBoost, Random Forest, and a Neural Network—we simulate real-world design scenarios where parameter fine-tuning may not always be feasible. Key tasks include predicting layout performance from schematic data, performance prediction across process corners, and fabricated chip performance. Our results show that these models can achieve less than 5% mean absolute percentage error (MAPE) for power and frequency prediction while reducing required simulations by more than$2\times $. When migrating from 14nm to 5nm, XGBoost and Neural Network achieve high accuracy (>0.99$R^{2}$) using just 10% of the otherwise required 5nm simulations. We also present an extensive robustness analysis to demonstrate that our results are not limited to a single data split or initialization. By varying random seeds across multiple runs, we evaluate the stability of each model with respect to algorithm initialization and the selection of training data subsets. This demonstrates that the observed accuracy is consistent and not the result of a specific, favorable configuration. This framework offers a promising approach to accelerating circuit design across technology nodes by reducing simulation costs while maintaining accuracy in predicting performance. Dimple Vijay Kochar, Maitreyi Ashok, John Cohn, Xin Zhang 0025, Anantha P. Chandrakasan |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2025 | Heterogeneously Integrated Nitrogen-Vacancy Sensing for Real-Time CMOS Security Threat DetectionabstractThis work proposes a prototype system for utilizing nitrogen-vacancy center-based quantum sensing for generalized threat detection systems. Changes to the operation or environment of an IC will cause differences in the magnetic field emanations, which can be detected through changes in a spin-state-dependent photocurrent within a diamond. Threat detection circuitry can be integrated within the sensitive CMOS IC itself at a high spatial resolution for real-time monitoring and spatially resolved low-overhead protections. The key contributions of this work are the CMOS and NV center system for high magnetometer sensitivity while maintaining CMOS design flexibility, the novel security application for quantum sensing, and the proposed method of heterogeneous integration for a complete system. Maitreyi Ashok, Hanfeng Wang, Ethan G. Arnault, Hamza Raniwala, Aya G. Amer, Matthew Trusheim, Dirk R. Englund, Anantha P. Chandrakasan |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2022 | Hardware Trojan Detection Using Unsupervised Deep Learning on Quantum Diamond Microscope Magnetic Field ImagesabstractThis article presents a method for hardware trojan detection in integrated circuits. Unsupervised deep learning is used to classify wide field-of-view (4 × 4 mm 2 ), high spatial resolution magnetic field images taken using a Quantum Diamond Microscope (QDM). QDM magnetic imaging is enhanced using quantum control techniques and improved diamond material to increase magnetic field sensitivity by a factor of 4 and measurement speed by a factor of 16 over previous demonstrations. These upgrades facilitate the first demonstration of QDM magnetic field measurement for hardware trojan detection. Unsupervised convolutional neural networks and clustering are used to infer trojan presence from unlabeled data sets of 600 × 600 pixel magnetic field images without human bias. This analysis is shown to be more accurate than principal component analysis for distinguishing between field programmable gate arrays configured with trojan-free and trojan-inserted logic. This framework is tested on a set of scalable trojans that we developed and measured with the QDM. Scalable and TrustHub trojans are detectable down to a minimum trojan trigger size of 0.5% of the total logic. The trojan detection framework can be used for golden-chip-free detection, since knowledge of the chips’ identities is only used to evaluate detection accuracy. Maitreyi Ashok, Ronald L. Walsworth, Edlyn V. Levine, Anantha P. Chandrakasan |
ACM J. Emerg. Technol. Comput. Syst. | 1 |
| 2019 | Deep Multi-State Dynamic Recurrent Neural Networks Operating on Wavelet Based Neural Features for Robust Brain Machine InterfacesabstractWe present a new deep multi-state Dynamic Recurrent Neural Network (DRNN) architecture for Brain Machine Interface (BMI) applications. Our DRNN is used to predict Cartesian representation of a computer cursor movement kinematics from open-loop neural data recorded from the posterior parietal cortex (PPC) of a human subject in a BMI system. We design the algorithm to achieve a reasonable trade-off between performance and robustness, and we constrain memory usage in favor of future hardware implementation. We feed the predictions of the network back to the input to improve prediction performance and robustness. We apply a scheduled sampling approach to the model in order to solve a statistical distribution mismatch between the ground truth and predictions. Additionally, we configure a small DRNN to operate with a short history of input, reducing the required buffering of input data and number of memory accesses. This configuration lowers the expected power consumption in a neural network accelerator. Operating on wavelet-based neural features, we show that the average performance of DRNN surpasses other state-of-the-art methods in the literature on both single- and multi-day data recorded over 43 days. Results show that multi-state DRNN has the potential to model the nonlinear relationships between the neural data and kinematics for robust BMIs. Benyamin Allahgholizadeh Haghi, Spencer S. Kellis, Sahil Shah, Maitreyi Ashok, Luke Bashford, Daniel Kramer, Brian C. Lee, Charles Liu, Richard A. Andersen, Azita Emami-Neyestanak |
NeurIPS | 4 |