The integrated sensing and communication (ISAC) gives the new paradigm for the secure communication design. In this paper, the dual-functional radar communication (DFRC) enabled physical layer security (PLS) is investigated. Specifically, we propose the novel Cramér-Rao bound (CRB) based statistical imperfect channel state information (CSIC) model, which integrates the radar CRB into the statistical imperfect CSI model based on the second-order moment. Further, the CSIC based PLS optimization model is proposed, where the expectation of the secrecy rate is maximized under the PLS requirement and the radar CRB based constraint. The corresponding CSIC semidefinite relaxation (CSIC-SDR) based iteration algorithm is developed to achieve the beamforming design with the aid of one-dimension search of the optimal CRB based sensing measure. Numerical results demonstrate that the proposed CSIC-SDR outperforms the norm-bound CSI based and circularly symmetric complex Gaussian distribution CSI based beamforming designs in terms of the PLS performance.

Integrated sensing and communication (ISAC) enables several emerging applications while suffering severe security issues. In this article, the novel illegal sensing suppression (ISS) is proposed to protect the privacy of the specific legitimate user in the presence of an adversary with the sensing capacity in the ISAC system. The target detection and the direction of arrival estimation as common sensing tasks are investigated to deteriorate the sensing performance at the adversary side. To this end, we propose the missed detection probability maximization and the Cramér-Rao bound (CRB) maximization-based ISS model. This model also ensures the achievable rate and the legitimate sensing CRB toward the adversary at the ISAC base station side. The beamforming optimization algorithms are developed based on the alternating optimization and semidefinite relaxation techniques in order to address the nonconvex issue in the formulated ISS models and explore the rate-ISS tradeoff in the ISAC system. We further propose the closed-form solution for the single user case in the target detection suppression scenario. Numerical results demonstrate the necessity of the ISS and the ISS gain of proposed algorithms compared with other baseline schemes.

This brief presents a current-steering 25-GS/s 8-bit digital-to-analog converter (DAC) based on a 40-nm CMOS technology. The DAC employs a dual-edge sampling (DES) architecture to reduce the requirement of main clock frequency, optimizing switching noise and improving power efficiency. DES is sensitive to the clock duty cycle. To minimize the image tones and performance degradation caused by duty-cycle errors, a single-slope analog-to-digital converter (ADC)-based duty-cycle detection and correction scheme is proposed, achieving closed-loop background calibration. A T-coil output network is used to extend the bandwidth. The proposed DAC achieves a spurious-free dynamic range (SFDR) of >40 dBc up to the Nyquist frequency and a >12-GHz output bandwidth with sinc roll-off compensation. The active power consumption is about 272 mW under 1.8-/0.9-/−1.8-V power supply.

This brief reports on a 13-GHz quad-core voltage-controlled oscillator (VCO) using a folded S-shaped tail inductor. The contribution of this work is that the auxiliary resonator is folded into the main inductor, so that it leads to a more compact solution than a conventional scheme. Due to the S-shaped inductor’s electromagnetic (EM) characteristics, the proposed tail filter can achieve noise suppression without EM interference to the main tank. Designed and implemented in a 28-nm CMOS process, the proposed VCO operates between 12.32 and 13.84 GHz, for an 11.6% turning range. The measurements were carried out in the free-running mode, and the results show a phase noise (PN) of 118.3 dBc/Hz at a 1-MHz offset from the central frequency of 12.32 GHz. The power consumption of the VCO core is 24.5 mW, with a 0.9-V supply voltage, and this leads to a figure of merit (FoM) of 186.6 dBc/Hz.

This brief presents an explicit Class-F23 voltage-controlled oscillator (VCO). The square-like voltage waveform is obtained via waveform shaping, and flicker noise upconversion is suppressed by a proper common-mode (CM) return path. CM resonance at the second harmonic frequency is introduced by a compact octagonal inductor. The rms value of the impulse sensitivity function (ISF) is significantly reduced through Class-F23 operation. The VCO switches between two modes of a high-order LC resonator consisting of two identical LC tanks coupled by capacitors. A prototype of the VCO is implemented in a 28-nm CMOS. Measurements show a continuous tuning range (TR) of 4.89–7.29 GHz, with a peak figure of merit (FoM) of 190.5 dB/Hz at 5.8 GHz and better than 188.5 dB across the entire TR. The flicker phase-noise corner ranges from 70 to 400 kHz. The VCO consumes 16–19 mW from a 0.5-V supply and occupies an active area of 0.21 mm2.