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Hanpeng Xiao

dblp:256/0806 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 87% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant processor arrays		 0.412020
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware reliability and fault tolerance › reconfiguration
topology reconfiguration		 0.412020
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Interconnection networks and networks-on-chip
3d network-on-chip		 0.112020
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

heuristic algorithm · 0.4flexible rerouting scheme · 0.4
YearPublicationVenuePosition
2020 Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays
abstract
In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.
Junyan Qian, Hao Ding 0007, Hanpeng Xiao, Zhide Zhou, Lingzhong Zhao, Zhongyi Zhai
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3