Demo Data from EDBT 2026 / reviewers in the wild / expert
Alexis Lescouet
dblp:256/0869
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 62% Parallel and multicore computing · 19% Processor architecture and microarchitecture · 19% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
profiling |
0.4 | 1 | 2019 | Using Differential Execution Analysis to Identify Thread Interference · IEEE Trans. Parallel Distributed Syst. 2019 |
Parallel and multicore computing › parallel computing › parallel application performance
multithreaded application performance |
0.1 | 1 | 2019 | Using Differential Execution Analysis to Identify Thread Interference · IEEE Trans. Parallel Distributed Syst. 2019 |
Processor architecture and microarchitecture
resource contention |
0.1 | 1 | 2019 | Using Differential Execution Analysis to Identify Thread Interference · IEEE Trans. Parallel Distributed Syst. 2019 |
Methods — techniques the papers use, named apart from their topics
performance variation metric · 0.4differential execution analysis · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Using Differential Execution Analysis to Identify Thread InterferenceabstractUnderstanding the performance of a multi-threaded application is difficult. The threads interfere when they access the same shared resource, which slows down their execution. Unfortunately, current profiling tools report the hardware components or the synchronization primitives that saturate, but they cannot tell if the saturation is the cause of a performance bottleneck. In this paper, we propose a holistic metric able to pinpoint the blocks of code that suffer interference the most, regardless of the interference cause. Our metric uses performance variation as a universal indicator of interference problems. With an evaluation of 27 applications we show that our metric can identify interference problems caused by six different kinds of interference in nine applications. We are able to easily remove seven of the bottlenecks, which leads to a performance improvement of up to nine times. Mohamed Said Mosli Bouksiaa, François Trahay, Alexis Lescouet, Gauthier Voron, Rémi Dulong, Amina Guermouche, Elisabeth Brunet, Gaël Thomas 0001 |
IEEE Trans. Parallel Distributed Syst. | 3 |