This paper demonstrates a 12-bit 100-MS/s PVT-stabilized pipelined-SAR ADC with fully integrated on-chip calibration. Two key innovations facilitate over 65-dB SNDR with less than 2.2-dB variation from -20 °C to 125 °C: First, a PVT-stabilized nested negative-C topology boosts open-loop gain ($G_{ol}$) of the residue amplifier (RA) by 28 dB, enabling one-time foreground calibration that avoids persistent inter-stage gain error tracking. Second, a dynamic auto-zeroing technique addresses offsets from both the RA and first-stage comparator through a switched-capacitor filter that extracts offsets based on the stochastic characteristics of residue signals. Dynamically level-shifted capacitors (DLSC) are embedded at the differential inputs to neutralize aliased noise and thermal noise, so that the offset drifts under high-temperature environment are effectively cancelled. Fabricated in 40-nm CMOS, the prototype occupies 0.22 mm2and achieves 65.5-dB SNDR and 83-dB SFDR at Nyquist input while consuming 3.7 mW. Across six tested chips, the prototype design exhibits merely 2.2-dB SNDR degradation over -20 °C ~ 125 °C and 1.3-dB variation under ± 5 % supply voltage (1.1 V) fluctuations.

A digital background calibration technique is proposed in this brief, utilizing comparator metastability to correct conversion errors from interstage gain errors and higher order nonlinearities for the first time. The method calibrates nonlinear conversion errors by injecting multilevel dithers and observing amplifier gain variations. It offers advantages, such as simple design, high accuracy, fast convergence, and low power consumption. Simulation results demonstrate the effectiveness of the technique, with the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) performances of a 14-bit two-stage pipelined successive approximation register analog-to-digital converter (SAR ADC) improving from 60.4 and 73.6 to 84.5 and 110.0 dB, respectively. The convergence speed of the calibration algorithm is 0.8 million samples.

This paper introduces a dual main clock generator (DMCG) and a digital serializer (DS) to improve the power efficiency of the time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines a dual-path front end and an improved selecting signal generator that addresses the potential phase error and reduces the peak current of the clock-driving circuits by 60%. The DS is proposed to serialize the digital outputs without employing power-hungry inverter-based buffer chains thus reducing the power consumption by 39.2%. The reference-free time skew extraction algorithm (RFA) is presented to mitigate the accuracy deterioration due to selecting the fixed middle channel. These techniques are validated by a prototype 12-bit 10-GS/s TI pipelined successive approximation register (TI-Pi-SAR) ADC. Fabricated in a 28-nm CMOS process, the prototype chip occupies an area of 4.4 mm2. The measurement results show that the ADC achieves a 49.8 dB SNDR and 60.0 dB SFDR after calibration at Nyquist frequency, while the total power consumption is 270 mW, leading to the figure of merits of Schreier (FoM$_{\mathrm {S}}$) and Walden (FoM$_{\mathrm {W}}$) of 152.5 dB and 106.9 fJ/conv.-step, respectively.