System-on-chip security architecture is a critical, complex, and time-consuming activity, consuming months of effort. Furthermore, the architectural design can include subtle errors that compromise the security of the entire system. In this article, we develop a security engine infrastructure, SEnTry , for systematically creating security architectures for protecting SoC designs against a variety of security subversions. SEnTry provides a plug-and-play, configurable subsystem composed of custom IPs that can be integrated into the platform to derive different security primitives. We develop an instance of SEnTry for supply-chain attacks. We discuss the spectrum of challenges involved in developing a unified architecture for systematic protection against the variety of attacks involved and the SEnTry approach to addressing them. We provide several case studies to demonstrate SEnTry design and perform extensive experiments to evaluate its overhead on multiple ASIC technologies. Our experiments suggest that SEnTry incurs minimal overhead in area and power consumption.

The horizontal business model of modern semiconductors—where design, fabrication, and testing are handled by separate entities across a global supply chain—exposes integrated circuits (ICs) to various security threats throughout their lifecycle. Physical unclonable functions (PUFs) have emerged as effective hardware security primitives for device identification and attestation. However, integrating PUFs into existing designs is often manual, labor-intensive, and incurs high overhead in area, power, and design time. Moreover, traditional PUFs are typically localized to small regions of a chip, limiting entropy extraction from the full design surface. To address these limitations, we propose ASTRA, an automated framework that integrates PUF-based entropy sources into digital logic circuits in a distributed and timing-aware fashion. ASTRA enhances the conventional logic synthesis flow by inserting memory-in-logic PUFs (MeLPUFs), which are constructed using standard cell elements and offer high entropy. By distributing MeLPUF primitives across the circuit, ASTRA maximizes response randomness while minimizing area and power overhead. It can also reuse existing logic elements and supports multiple MeLPUF templates. ASTRA ensures timing constraints are respected and enables validation of both functional and logic equivalence checking (LEC) between the original and PUF-inserted designs. Experimental results show that ASTRA achieves near-ideal PUF quality metrics, demonstrating its effectiveness and scalability for secure hardware design.

Modern system-on-chip (SoC) designs are increasingly vulnerable to supply chain threats such as counterfeiting, overproduction, and reverse engineering, leading to financial losses, intellectual property (IP) theft, and compromised system integrity. Existing security engines, while effective in principle, typically rely on microcontroller-based architectures that incur significant area and power overhead, making them impractical for resource-constrained devices. In this article, we present a minimally configured security engine (MCSE), a lightweight, modular, configurable security engine designed to address the most critical supply-chain threats with minimal resource consumption. We introduce the notion ofminimum security, a baseline set of protection features necessary to secure SoCs under strict area and power constraints, and demonstrate how MCSE can be tailored to meet diverse system requirements. We validate our architecture through implementation on multiple ASIC technology nodes, showing favorable tradeoffs between security capability, area, and power. Our results establish MCSE as a compelling solution for integrating supply chain protection into low-power and area-sensitive SoC designs.

Physical Unclonable Functions (PUFs) have emerged as promising hardware security primitives to protect embedded systems from various attacks throughout their life cycle. Field Programmable Gate Arrays (FPGAs), increasingly used in embedded platforms due to their reconfigurability and performance, offer an ideal fabric for implementing PUFs. However, existing FPGA-based PUFs either incur high resource overhead or suffer from limited entropy quality. This work presents MARVEL-PUF, a novel multi-bit memory-based PUF architecture implemented using LUTs within FPGA hardware. MARVEL-PUF emulates modified SRAM cells using cross-coupled LUT-based inverters and introduces a precharge mechanism that drives the feedback loop into a high-energy metastable state before resolving to a stable response. This enables dynamic and reliable signature generation even under environmental noise. Additionally, the use of multiplexed paths expands the challenge-response space, transforming a weak memory PUF into a strong and reconfigurable security primitive. Experimental results on commercial FPGAs demonstrate that MARVEL-PUF achieves high entropy density and near-ideal values for uniqueness, robustness, uniformity, and correlation. These properties make it a strong candidate for low-overhead security in embedded applications. Future work will explore template scaling and side-channel attack resilience.

Scan-Based Design-For-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITEfor design modifications. We show that LITEsignificantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions.

Rapid adoption of AI technologies raises several major security concerns, including the risks of adversarial perturbations, which threaten the confidentiality and integrity of AI applications. Protecting AI hardware from misuse and diverse security threats is a challenging task. To address this challenge, we propose SAMURAI, a novel framework for safeguarding against malicious usage of AI hardware and its resilience to attacks. SAMURAI introduces an AI Performance Counter (APC) for tracking dynamic behavior of an AI model coupled with an on-chip Machine Learning (ML) analysis engine, known as TANTO (Trained Anomaly Inspection Through Trace Observation). APC records the runtime profile of the low-level hardware events of different AI operations. Subsequently, the summary information recorded by the APC is processed by TANTO to efficiently identify potential security breaches and ensure secure, responsible use of AI. SAMURAI enables real-time detection of security threats and misuse without relying on traditional software-based solutions that require model integration.Experimental results demonstrate that SAMURAI achieves up to 97% accuracy in detecting adversarial attacks with moderate overhead on various AI models, significantly outperforming conventional software-based approaches. It enhances security and regulatory compliance, providing a comprehensive solution for safeguarding AI against emergent threats.

The capability of artificial intelligence (AI), increasingly embedded in critical domains, faces a complex array of security threats. It has motivated researchers to explore the security vulnerability of AI solutions and propose effective countermeasures. This article offers a comprehensive exploration of diverse attacks on AI models, including backdoors (Trojans), adversarial, fault injection, data poisoning, model inversion, model extraction, membership inference attacks, etc. These security vulnerabilities are classified into two broad categories, namely, Supply Chain Attacks and Runtime Attacks. We highlight threat models, attack strategies, and defenses to secure AI systems against these attacks. The work also underscores the significance of developing secure and robust AI models and their implementation to safeguard sensitive data and embedded systems. We present some emerging research directions on secure AI systems.

Securing intellectual property (IP) in hardware has become increasingly crucial amid increasing threats from adversaries due to untrusted entities in the integrated circuit (IC) supply chain. Hardware obfuscation techniques like logic locking and state-space transformation have emerged as potent countermeasures against such threats, but doubts about their efficacy persist due to compromises in recent years. Furthermore, existing countermeasures also tend to address specific adversarial threat models. This paper introduces LISA, a multi-layered framework that uses iterative unit transformations to address security concerns in hardware obfuscation at minimal overhead costs. The proposed framework employs a security-metric-guided analysis of obfuscated IPs, subjecting them to various attacks to uncover vulnerabilities. Once identified, LISA implements unit transformations that harden the obfuscation against these vulnerabilities. Compared to prior work, the layered iterative framework employed can thwart current and emerging threats by acquiring novel adaptive design transformations to minimize overhead incurred at each iteration. The proposed methodology is implemented using commercial EDA tools and evaluated on open-source ISCAS85 and MIT-CEP benchmarks, demonstrating promising attack resilience with low overheads.