Comparators have been optimized for quick decision-making and reduction of dynamic power consumption through years of research by incorporating strong positive feedback latches. However, these advancements can make double-tail dynamic comparators more susceptible to single-event effects (SEEs). In this work, we present a new comparator design that is hardened against these radiation effects. The proposed design is a modified version of a low-voltage, low-power double-tail comparator, designed in a 180 nm technology node, and it can achieve high levels of SEE tolerance with an acceptable degree of trade-off in area, delay, and power consumption. The proposed comparator is shown to have superior SEE tolerance compared to a radiation-hardened conventional double-tail comparator with a similar electrical performance designed in the same technology node, and the proposed design’s functionality is proven by post-layout simulations across extreme simulation corners, combining process corners with temperature and supply voltage variations.

The development of non-volatile Compute-In-Memory (nvCIM) technology has demonstrated significant potential in addressing the data movement and Multiply-and-Accumulate (MAC) bottlenecks in machine learning algorithms by enabling parallel analog Vector-Matrix Multiplication (VMM) operations directly within memory arrays. In this work, we introduce SPIKA, a fully integrated RRAM-CMOS chip designed for neural network acceleration. The key innovation of SPIKA lies in its ability to efficiently transfer input signals to output signals with minimal circuit overhead. The VMM operation is performed in the time domain, with the dot product accumulated on a switched capacitor, eliminating the need for high-resolution, power-intensive data converters. Implemented using commercially available 180nm technology, SPIKA operates on a 64×128 crossbar and utilizes 4-bit inputs, ternary weights, and 5-bit outputs. The chip is evaluated on the MNIST dataset, achieving a peak throughput of 1092 GOPS and an energy efficiency of 195 TOPS/W.

The Physical Unclonable Function (PUF) is a security mechanism that takes advantage of the physical variations in a device to create a unique response that can be used as a device signature or secure key. However, many DRAM-based PUFs violate the operating rules of commodity DRAM to exploit a source of entropy in the DRAM read path. This work proposes a fast and reliable DRAM-based PUF that evaluates the variation of adjacent cells and produces the response through the normal read operation. The proposed design is implemented using 65-nm technology, and a detailed statistical SPICE simulation verifies its validity. The statistical analysis shows that the proposed PUF achieves 54.19% uniformity and 49.43% uniqueness, with 98% of the investigated responses achieving a Shannon entropy of 0.95. Additionally, the proposed design generates the response by 45, which is at least 66.7 times faster than existing systems. Furthermore, the proposed design uses the relative behavior of cells, which allows for stable responses against temperature and voltage variations, eliminating the need for error correction codes. The proposed PUF also shows resiliency against machine learning-based modeling attacks, as the prediction accuracy does not exceed 55% over 5K Challenge-Response Pairs (CRPs). The area overhead is negligible as the proposed design uses standard circuits, with the addition of only one 2x1 multiplexer at the inputs of the row buffer.

True Random Number Generators (TRNGs) are used in a variety of applications including cryptography, computer simulation, gambling games, machine learning and hyperdimensional computing. Dynamic Random-Access Memory (DRAM)-based TRNGs have been widely used as they are low cost and available in most modern electronic devices. However, most existing DRAM-based TRNGs produce random numbers with either hardware overhead, or low throughput. In this work, we report a novel high dense, high throughput and high entropy DRAM-based TRNG, named DTRNG, that exploits the process variations inherited by the DRAM cell's access transistor and sense amplifiers. DTRNG can be employed in commodity DRAM chips with no hardware overhead and using the standard memory controller commands. The proposed method is based on controlling the word line voltage supply part of the DRAM chip during random number mode. The novel approach provided in this work has been validated using cadence circuit tools on a constructed 8x8 DRAM chip in 65nm technology. In addition, Monte Carlo simulations are performed to verify the entropy of the generated numbers. The random sequence generated by DTRNG has passed all the NIST test without any post-processing demonstrating randomness and suitability for security scheme. DTRNG is considered a milestone towards low cost and high efficient secure hardware for AI and IoT applications.