This work presents a novel configurable two-stage inverter-based ultra-low-power (ULP) OTA with digitally adjustable output stage for dynamic adjustments of gain-bandwidth product, (GBW) and average slew rate (${\mathbf {SR}}_{\mathbf {av}}$). This approach improves both the flexibility of the OTA compared to conventional DC-biased designs, providing a reliable solution for mitigating process, voltage, and temperature variations. The circuit is designed using standard cells in a 180-nm CMOS process and is then fully synthesizable. Experimental measurements are executed over process corners and voltage variations. The proposed OTA works at nominal 0.3-V power-supply voltage and consumes only 1.2 nW, while exhibiting 56-dB DC gain and 7.6-kHz maximum GBW with 5-pF capacitive load.

In this work,a novel bulk-driven OTA capable to operate with a supply voltage as low as 400mV is presented. The proposed single stage topology results in an increased differential gain of about 75dB, while guaranteeing a very low power consumption in the range of 1.8nW. The amplifier exploits a body-driven input stage with a current-mirror-based differential to single-ended converter. The gain of the OTA is boosted thanks to the adoption of a cascode configuration and of a positive feedback loop, which allows to increase the output resistance without adding additional current branches. The CMRR is also improved thanks to the adoption of a replica bias loop which takes track of common-mode voltage variations to adjust the common-mode current, resulting in a CMRR higher than 85dB. The circuit has been designed considering a 180nm CMOS technology from TSMC, and post-layout simulations in the Cadence Virtuoso environment have shown an excellent resilience of the proposed OTA to PVT variations.

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with supply voltages as low as 0.3V, maintaining stable power consumption through a reference bias current. The resulting PUF achieves remarkable energy efficiency, consuming only 0.3 fJ per bit, without compromising statistical performance. It exhibits a response bias of 49.42%, a reliability of 99.483%, and a uniqueness of 50.176%. Validation of this novel approach is conducted through simulations and measurements on a 130nm CMOS test-chip, considering a nominal supply voltage of 0.3V, ±10% supply voltage variations, and a temperature range from 0°C to 75°C. Rigorous experimental verification on 20 chip samples, along with detailed explanations of design methodologies, underscores the robustness and practicality of the proposed Body-PUF design. Comparative analyses against state-of-the-art literature reveal that the Body-PUF outperforms previous PUF designs in Figures of Merit (FOM), making it promising for real-world authentication scenarios. Its outstanding trade-off between performance and practicality positions it as a compelling solution for secure applications, including Internet of Things (IoT) devices and other security-critical systems.

This work presents a novel proposal for utilizing the latched ring oscillator (LRO) as a reconfigurable entropy source, outperforming the existing literature on both physical unclonable functions (PUFs) and true random number generators (TRNGs). The PUF working principle and mathematical model are proposed in this manuscript for the first time as well as its performance measured on FPGA. The proposed LRO-based PUF is$2\times $more compact than state-of-the-art PUFs on FPGA. The LRO TRNG architecture has been revisited, and an XOR-tree-based postprocessing technique has been introduced to increase the throughput from 0.76 up to 800 Mbit/s, paving the way for a novel class of high-throughput reconfigurable entropy sources. The results of NIST tests carried out also under supply voltage and temperature variations have demonstrated robust key extraction and secure random number generation for different applications. This comprehensive proposal aims to advance the state of the art in compact and high-throughput entropy sources, catering to the increasing demands of modern cryptographic hardware.

This paper presents a True Random Number Generator (TRNG) exploiting latched-XOR (LX) gates and its implementation on a Xilinx Spartan 6 FPGA device. The proposed LX-TRNG aims at improving the Throughput (TP) of conventional ring oscillators (ROs) based TRNGs by combining the effect of latches metastability and ROs jitter. Measurements results have demonstrated that the generated bitstreams show very good randomness exhibiting a byte (bit) entropy of 7.9979 (0.9997), according to T8-test of AIS-31. The proposed TRNG has also been extensively tested under voltage and temperature variations showing very good robustness. In particular both NIST’s and AIS-31 tests are passed for all the considered supply voltage and temperature ranges. The FPGA implementation occupies only 9 Slices and, despite its compactness, it exhibits a throughput as high as 12.5 Mbit/s with a 50 MHz operating frequency. The computation of the figure of merit$FOM_{E}$has shown the capability of the proposed TRNG to optimize the trade-off between hardware resources, bitstreams entropy and throughput, outperforming previous works.