Neuromorphic hardware combined with spiking neural networks (SNNs) supports low-power, highly parallel AI inference. Inference accuracy can drop sharply when models trained under ideal software assumptions are deployed on inherently noisy hardware. This noise is especially evident in the current of subthreshold operated charge-trap transistors (CTTs) representing network weights. Although CTTs are CMOS-compatible and attractive for large-scale neuromorphic systems due to their energy and cost efficiency, programming imprecision and process, voltage, and temperature (PVT) variations can significantly alter their current, degrading network accuracy. In this article, CTT weight and neuron sources of variability are first identified. Multiparameter noise models are then derived from the hardware components, and sampled noise is injected into both weights and neuron parameters during training, improving robustness across a wide range of noise levels without increasing model size or significantly increasing training time. A novel training algorithm is introduced in which each mini-batch is evaluated multiple times under different noise samples, with the loss optimized to enforce consistency across various noise values. The software behavioral model is verified using Cadence simulations across 45 binary classifiers. The accuracy of ideal-trained classifiers degrades by up to 44.2% under hardware-induced noise, while the proposed training algorithm improves accuracy by up to 23.34%. The validated framework and training algorithm are then used for larger networks performing image classification on CIFAR-10 and CIFAR-100 datasets, improving accuracy from a random state under noise to competitive levels relative to state-of-the-art, with the main overhead being additional epochs determined by noise range rather than network size.

This article presents a multiband low-power and low-complexity impulse radio ultrawideband (IR-UWB) noncoherent receiver. The proposed receiver can be digitally reconfigured in three different modes of operation, including two single-band modes and one concurrent dual-band mode. In the two single-band modes, the proposed envelope detection architecture is capable of receiving and demodulating an ON–OFF keying (OOK) pulse stream at RF center frequencies of 2.8 or 4.8 GHz. In the concurrent dual-band mode, the proposed architecture is able to demodulate binary frequency-shift keying (FSK), in addition to OOK demodulation, at center frequencies of 3 and 5 GHz. The receiver is composed of a reconfigurable low-power differential low noise amplifier (LNA), a fully differential squarer (self-mixer circuit), low-pass filter (LPF), and variable gain baseband (BB) amplifiers. The receiver is fabricated in TSMC 130-nm CMOS process technology. The receiver can operate at up to 150 Mb/s with the ternary signaling that is enabled by the binary FSK modulation combined with the OOK modulation in concurrent dual-band mode. At its maximum gain, the receiver achieves a sensitivity of −72 dBm at a bit error rate (BER) of$10^{-3}$at a 100-Mb/s data rate. It consumes 11.9 and 13.2 mW from a 1.2-V supply in the single-band modes and concurrent dual-band mode, respectively.

A blocker-tolerant harmonic selection receiver front-end with RF bandwidth of 6.5 GHz to support the fifth-generation (5G) sub-6 GHz band is presented. The proposed N-path switching filter-based receiver employs harmonic recombination blocks at the baseband (BB) to select the desired local oscillator (LO) harmonics and suppress blockers. It is demonstrated how the configuration of two feed-forward N-path switching filters and BB harmonic recombination stage can be reconfigured to select the first harmonic of the switching frequency at the low-frequency band (0.5–1.9 GHz) and the third LO harmonic at the high-frequency band (1.95–6 GHz). Thus, the proposed architecture has the capability of supporting an RF input frequency of up to 6 GHz while the switching frequency operates up to 2 GHz. Higher harmonic selection in addition to the fundamental helps to reduce the power consumption and required input frequency of the multiphase LO clock generator. An RF receiver prototype is fabricated in a TSMC 130-nm CMOS technology. It achieves a 5 dB noise figure (NF), −16.6 dBm in-band input-referred third-order intercept point (IIP3), and 9 dBm out-of-band (OOB) IIP3, respectively, at the low-frequency band (0.5–1.9 GHz). The 2nd–5th harmonic rejection ratios (HRRs) are higher than 44 dB without any calibration. The receiver can tolerate a 0 dBm blocker at a 180 MHz offset from a 1 GHz switching frequency with an NF of 9.4 dB. Over the high-frequency band (1.95–6 GHz), the receiver’s NF is less than 7.1 dB. Moreover, in-band IIP3, OOB IIP3, and first HRR are higher than −21 dBm, 7 dBm, and 39 dB, respectively. The receiver achieves an S11 better than −10 dB over 0.5–6 GHz, and has a total power consumption of 17–22.5 mW from a 1.2 V supply.

$N$-path switching systems using switched-series R-C networks are analyzed in the context of RF receiver front-ends, and it is shown that it is possible to mitigate the need to generate an accurate low power clock at high frequencies by operating at higher order harmonics of the switching frequency. For values of$N$that are an integer factor of 4 (i.e.,$N$= 4, 8, and 16), harmonic selection RF receivers’ architectures are presented using two feed-forward$N$-path switching filters and harmonic recombination at the baseband. Moreover, it is demonstrated how the harmonic recombination stage at the baseband can be reconfigured to select the third harmonic of the switching frequency rather than the fundamental to reduce the input frequency and power consumption of the multi-phase clock generator by a factor of 3. In addition, to analyze the performance of the proposed RF receiver architecture, multiple receivers have been designed and post-layout simulated in two CMOS technologies, TSMC 130 nm and TSMC 65 nm. The resulting 5.7–7.2-GHz RF receiver architectures allow for operation at the third harmonic of the LO frequency (i.e., 1.9–2.4 GHz), reducing power consumption and allowing for good performance metrics at both studied technology nodes.