Digital ΔΣ modulators (DDSM) are used in applications that require a reduction of the wordlength of a digital signal. In the presence of non-idealities, the quantization error of the DDSM can interact with nonlinearities further along the signal chain and generate spurious tones in addition to excess noise. This paper introduces the INIS family of DDSMs that are inherently immune from nonlinearity-induced spurs. Some representative members of the family are analyzed through simulations; one is demonstrated with a hardware implementation. Their performances are compared with those of other well-known DDSM architectures.

Phase locked loops for fractional frequency synthesis typically use Digital$\Delta \Sigma $Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional-${N}$frequency synthesizers with polynomial nonlinearities.

Spurious tones appear in the output phase noise spectrum of a fractional-N frequency synthesizer when nonlinearities are present in the loop. These spurs are generated by the interaction between the nonlinearity and the quantization error that the digital Σ modulator (DDSM) introduces into the system. This paper analyzes the spurious effect of polynomial nonlinearities on fractional-N CP-PLLs equipped with multi-stage noise shaping (MASH) DDSMs of different orders. This leads to a proof of immunity from spurs for PLLs based on higher order MASH modulators in the case of certain polynomial nonlinearities.

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital$\Delta \Sigma $modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results.