This paper presents the design of a 128 GS/s 64x time-interleaved SAR ADC, featuring an ultra-wideband two-rank hierarchical track-and-hold architecture maintaining 62 GHz bandwidth in 22nm CMOS FD-SOI technology. To achieve both, high bandwidth and concurrently adequate sampling linearity, an inductively peaked input network and first-stage source follower with pseudo-differential gain coupling is used, taking advantage of a dual -0.5V and 0.9V power supply. The front-end T/H also utilizes a mix of static and dynamic body-biasing techniques enabled by the 22nm CMOS SOI technology to further improve the linearity and signal gain. Each second-level buffer drives four 6-bit asynchronous loop-unrolled SAR ADCs at a conversion rate of 2 GS/s, using speed-optimized dynamic logic cells and MDAC redundancy to fulfil the sampling speed requirements. Time-interleaving mismatch effects such as gain, offset and sample skew errors are calibrated off-chip. The total signal bandwidth across the input network, first-level buffer and T/H stage exceeds 62.2/53.9 GHz and the ADC achieves a SNDR of well above 35.5/32.3 dB up to 19.7 GHz as well as 31.7/28.6 dB up to Nyquist-frequency in TT/SS corner.

This paper presents the architecture and implementation of a low-noise sub-sampling phase-locked loop (SSPLL) for mm-wave frequencies. It leverages an LC oscillator with a novel resonator, a digital lock assist and frequency calibration system as well as a novel charge pump implementation. The charge pump eliminates the pulser and runs continuously, which significantly reduces its power consumption while maintaining equal noise performance. The calibration system solves the lock problem of the SSPLL by implementing a lock/frequency search to prevent non- and false-lock. The LC oscillator employs an optimized resonator which combines both the inductor and the capacitor on the same metal, resulting in a very high quality factor by eliminating the interconnect resistance within the resonator. The SSPLL was implemented and simulated in a 22-nm-FDSOI technology, alongside with measurement results of the LC oscillator, which was fabricated in the same technology.

This paper presents an 11-bit 12GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30fs step-size. The ADC achieves a voltage gain of 8.55dB in steering direction. An overall SFDR and SNDR above 68dBc and 55dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.

Next-generation data centers demand higher bandwidth, generating interest in 224 Gbit/s wireline transceivers. This paper analyzes the performance of PAM-4/PAM-6/PAM-8 for a co-packaged optical link including different channel lengths at 224 Gbit/s with all transceiver blocks, DSP equalization, and NEXT/FEXT crosstalk. With a 32-tap FFE and 1-tap MLSE equalization, a SER−3is achievable for PAM-4/PAM-6 for a channel attenuation <13dB at 56 GHz. Furthermore, a detailed power analysis is done for the modulations including all relevant transceiver blocks.

In this article, an overview of the most recent fully-depleted silicon on insulator technology (FD-SOI) design techniques in the field of mixed-signal circuits and systems are given. Cutting edge performance is achieved by using dynamic as well as static body-biasing techniques. 22FDX®is a 22nm CMOS FD-SOI technology providing both, a unique wide-band body-bias tuning range in conjunction with minimized parasitic device loads, due to the significant reduced pn junctions in the signal path. As a result, transistor transit frequencies exceeding 400GHz with improved linearity is achieved. With a linear threshold voltage sensitivity of around 75mV per Volt, 22FDX®gives designers a competitive additional degree of freedom. After introducing 22FDX®, a 5-bit 18.5GS/s flash ADC is presented utilizing body-biasing to generate accurate threshold voltage offsets within the comparators and thus omitting a power-hungry resistive ladder. Then, dynamic body-biasing is used for a 1.5GS/s track-and-hold circuit to improve the bandwidth while the leakage is reduced obtaining 80dBc SFDR up to the fourth Nyquist zone. Furthermore, a 26GHz ring oscillator is presented, which utilize the strong threshold voltage sensitivity to fully compensate corner dependency. Finally, a body-biasing controlled DAC linearization technique for multi-bit Sigma-Delta modulators enabling 90dBc SFDR, as well as a DAC driver termination impedance control for a 6GS/s 10-bit automotive Ethernet SST-DAC-Driver are presented.

This paper presents a calibration technique that corrects errors introduced by the current-steering feedback DAC within CT-SDMs. Thanks to the extensive and linear back-gate sensitivity on the threshold voltage, the 22FDX technology enables a full correction of the DAC cell errors by adaptively tuning the back-gate voltage of each current source via an auxiliary DAC (AUX-DAC). In contrast to state-of-the-art analog DAC error corrections, the proposed adaptive body-biasing correction places the AUX-DACs outside of the feedback loop. Hence, the statically operating AUX-DACs enable a highly area- and power-efficient DAC linearization technique. Based on a detailed feedback DAC mismatch analysis, the required AUX-DAC resolution and range is deducted. In addition, potential kickback from the feedback DAC to the AUX-DACs as well as the AUX-DAC noise contribution to the total modulator noise are discussed on schematic level. Eventually, extensive system-level simulations that model and compensate random DAC weight mismatch verify the presented theoretical analysis.

In this paper a novel sampler that performs beam-forming is introduced. Several parts of the receiver chain are combined into one compact sub-sampling beam-forming summation track and hold (SSBS-TH). It directly integrates a true time delay with a phase correct summation unit. Furthermore the proposed circuit includes the sampling capacitance of a time interleaved (TI) analog-to-digital converter (ADC). The SSBS-TH operates at 12 GS/s to enable wide-band operation and cover frequencies up to 6 GHz. Therefore it is suitable for software defined radio (SDR). An overall linearity of 56 dBc and a signal-to-noise ratio (SNR) above 52.8 dB is achieved.