This paper presents a low-noise class-F23voltage-controlled oscillator (VCO) with harmonic resonance expansion and$2^{\mathrm {nd}}$/$3^{\mathrm {rd}}$-harmonic outputs for multiband mm-wave applications. By using a single four-coil transformer to extend the common-mode (CM) and differential-mode (DM) harmonic resonance bandwidths, the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic resonances can be acquired without additional frequency alignment calibration. Meanwhile, benefiting from the favorable differential response at the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic frequencies, the corresponding harmonic frequency outputs are extracted, simultaneously. Fabricated in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range (FTR) of 20.8% from 10.71 GHz to 13.20GHz with 1-MHz offset phase noise (PN) from -117.4 to -114.5 dBc/Hz, while consuming 7.8-9.8 mW at 0.6 V. The VCO core area is only 0.054 mm2and the flicker noise corner is 310-450 kHz. The figure-of-merit (FoM) at 10-MHz offset scores 189.8-191.7 dBc/Hz. The harmonic outputs achieve a FTR of 21.42-26.40 GHz and 32.13-39.60 GHz, with a 1-MHz-offset PN from –110.5 to –107.5 dBc/Hz and –107.6 to –104.8 dBc/Hz.

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

This paper presents an integer-N sampling phase-locked loop (S-PLL) characterized by both low jitter and low spur. The design integrates a high-gain double-edge sampling phase detector (PD) and a self-retimed multi-modulus divider (MMD) aimed at mitigating the in-band noise. Furthermore, it features a compact implicit common-mode voltage-controlled oscillator (VCO) with a second harmonic tuning tailored for noise reduction. The proposed S-PLL, fabricated in a 28-nm CMOS technology, operates at 31 GHz with a 250-MHz reference. The measured RMS jitter is 39.69 fs integrated from 10 kHz to 100 MHz, with a reference spur of −63.2 dBc. The proposed PLL achieves a figure-of-merit (FoM) of −253.6 dB with a 28-mW power and a 0.047-mm2area.