Demo Data from EDBT 2026 / reviewers in the wild / expert
Won Jeon
dblp:257/5463
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 56% Storage systems · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › computational storage
in-storage computing |
0.4 | 1 | 2020 | REACT: Scalable and High-Performance Regular Expression Pattern Matching Accelerator for In-Storage Processing · IEEE Trans. Parallel Distributed Syst. 2020 |
Hardware accelerators and domain-specific architectures › pattern matching accelerator
regular expression matching accelerator |
0.4 | 1 | 2020 | REACT: Scalable and High-Performance Regular Expression Pattern Matching Accelerator for In-Storage Processing · IEEE Trans. Parallel Distributed Syst. 2020 |
Hardware accelerators and domain-specific architectures
pattern matching accelerator |
0.1 | 1 | 2020 | REACT: Scalable and High-Performance Regular Expression Pattern Matching Accelerator for In-Storage Processing · IEEE Trans. Parallel Distributed Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
parallel processing architecture · 0.4data access scheduling · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | REACT: Scalable and High-Performance Regular Expression Pattern Matching Accelerator for In-Storage ProcessingabstractThis article proposes REACT, a regular expression matching accelerator, which can be embedded in a modern Solid-State Drive (SSD) and a novel data access scheduling algorithm for high matching throughput. Specifically, REACT, including our data access scheduling algorithm, increases the utilization of SSD and the degree of internal memory parallelism for pattern matching processes. While the low-level flash exhibits long latency, modern SSDs in practice achieve high I/O performance by utilizing the massive internal parallelism at the system-level. However, exploiting the parallelism is limited for pattern matching since the subblocks, which constitute an input data and can be placed in multiple flash pages, should be tested in a sequence to process the input correctly. This limitation can induce low utilization of the accelerator. To address this challenge, the proposed REACT simultaneously processes multiple input streams with a parallel processing architecture to maximize matching throughput by hiding the long and irregular latency. The scheduling algorithm finds a data stream which requires a sub-block in closest time and prioritizes the access request to reduce the data stall of REACT. REACT achieves maximum 22.6 percent of matching throughput improvement on a 16channel high-performance SSD compared to the accelerator without the proposed scheduling algorithm. Won Seob Jeong, Changmin Lee 0002, Keunsoo Kim, Myung Kuk Yoon, Won Jeon, Myoungsoo Jung, Won Woo Ro |
IEEE Trans. Parallel Distributed Syst. | 5 |