This paper explores the application of reinforcement learning algorithms to the problem of calibrating and optimizing the performance of an integrated millimeter-wave (mmW) power amplifier (PA). The proposed calibration algorithm is aimed at compensating performance degradation while optimizing power efficiency, by finding the optimum values of a set of on-chip tuning knobs. The developed calibration solution is based on a multiagent deep reinforcement learning algorithm, in which a number of reinforcement learning agents learn to collaborate in order to optimize the complete set of specifications of the circuit under calibration. The proposed technique is validated based on post-layout simulation results of a tunable 60 GHz PA case study implemented in STMicroelectronics 55 nm CMOS technology.

This work presents a novel Single Capacitively Coupled (SCC) ring Voltage-Controlled Oscillator (VCO) designed for wideband N-path systems. It reduces the number of capacitors by half compared to the Double Capacitively Coupled (DCC) design, potentially requiring less silicon area while maintaining improved phase noise performance compared to the pseudo differential ring VCO, and with less power consumption than the DCC design. The proposed SCC VCO, tunable from 0.3 to 3.0 GHz, achieves the lowest power consumption among the state-of-the-art designs compared, consuming just 0.48 mW at 3 GHz, with a phase noise of -76.5 dBc/Hz at 1 MHz offset. Consequently, the figure of merit (FOM) remains modest at -147 dBc/Hz, comparable to other designs but leaving room for improvement. The analysis reveals that improper configuration may lead to unwanted oscillation modes of the three VCOs analyzed, making a startup circuit essential for stable operation. These results position the SCC ring VCO as a promising candidate for low-power, high-performance applications.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the$7^{th}$local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the$3^{rd}$,$5^{th}$, and$7^{th}$LO harmonics, 13 dB gain, 13.3 dB NF, −3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of$0.62\times 0.22~mm^{2}$.

This article proposes a general approach to accurately model the N-path filters and mixers, with the double purpose of bringing a better insight in the frequency transposition phenomena and opening the door towards a more general discussion concerning NPF-NPM and their outstanding properties as passive circuits. Thanks to a Fourier transform analysis, some mathematical equations are rigorously derived for both filtering and mixing voltage gains. The analysis is compared with ideal simulations for various sets of parameters: source impedance$R_{a}$, load impedance$R_{L}$, switch resistance$R_{sw}$, capacitive path$C_{L}$. Some error curves are extracted validating the initial hypotheses for the model in a given range of capacitances values. As a proof of concept, it is shown that the model complies with the measurements results with very good accuracy. The error is less than 10.5% on the two first harmonics prediction.

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ($\mathrm {P}_{\mathrm {DC}}$), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs$\ge80$GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ($\mathrm {P}_{\mathrm {DC}}$) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per$\mathrm {P}_{\mathrm {DC}}$(${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$) of 6.01 GHz/mW while being power-efficient.