The paper presents a voltage scalable dynamic-cum-body bias (DB+BB) comparator that uses a degeneration capacitor to prevent complete discharge of the pre-amplifier (pAmp) output nodes. An on-chip controlled bias is provided to the body of input-pair transistors that lowers the threshold voltage, and elongates the charge integration time. It augments the pAmp gain, and reduces the input-referred noise (IRN) and the overall delay. The post-layout simulations in 180nm silicon-on-insulator(SOI) technology demonstrate that the proposed DB+BB pAmp achieves 168.4µV IRN while consuming only 55.52fJ energy per comparison. The proposed comparator achieves a figure-of-merit of 5.3nJ·µV2·ns at 100MHz and 1.2V supply.

The paper presents power supply induced jitter (PSIJ) analysis of a latch based differential CMOS bootstrapped driver, designed for radiation hard particle detection application. The energy efficient driver circuit consists of bootstrap capacitor, boosted node voltages and reduced number of transistors to enhance the gate voltage for better driving efficiency. The closed-form transfer function of the design is derived to analyse the PSIJ. The circuit has been designed in a 180 nm silicon-on-insulator (SOI) technology for its inherent radiation hard by design (RHBD) characteristics with VDDof 0.9 V and input frequency of 40 MHz. The worst case PSIJ of the driver circuit is 1.65 ps with ±10% of supply fluctuations. The mathematical model for the design shows a good matching with the simulation and exhibits 13% of mean percentage error (MPE).