Deploying AI-based emotion recognition at the edge enables real-world applications but is constrained by data scarcity, heavy models, hardware limits, and privacy issues. To overcome these, we propose CHEER (Cloud-HEavy to Edge-Ready), a self-supervised, transfer-efficient framework where the cloud pre-trains lightweight graph-based encoders using unlabeled data, stores them as frozen models, and deploys only the needed encoder. New users are locally matched via centroids of clusters, and a small on-device classifier is trained with minimal labeled data, reducing computation, memory, and energy use while preserving privacy. Experimental results in the WEMAC and WESAD datasets show an accuracy of 78.19% and 80.08% at the edge on a NVIDIA Jetson Orin Nano. Moreover, CHEER achieves more than 60% reduction in model size, and lowers both peak RAM usage and energy consumption by more than 50% compared to the state-of-the-art.

The growing interest in affective computing has resulted in substantial advancements in emotion recognition through the application of various machine learning and deep learning techniques. Nevertheless, existing methodologies exhibit notable limitations. Specifically, they often fail to address extreme-edge design requirements, making them unfeasible for deployment in wearable systems under real-world conditions. With this aim, this paper introduces a novel end-to-end fear recognition system based on physiological signals designed specifically for deployment in extreme-edge contexts. This solution combines advanced feature engineering techniques with optimized lightweight 1D-CNN model architecture that integrates the advantages of both hand-crafted features and advanced deep-learning convolutional techniques. An experimental validation conducted with the WEMAC dataset provides f1-scores of 80% and accuracy rates of 74%, and reveals significant performance improvements with respect to our previous model proposed: 11.6% and 26.4% in accuracy and F1-score metrics, respectively. Additionally, this research demonstrates the successful integration and validation of the model within an ultra-low-power ARM Cortex™-M4 architecture, which exhibits an average power consumption of 16 mW at 5 V, with each inference requiring 496 ms. These results pave the way to a sustainable implementation of deep learning solutions in extreme-edge devices.

Deep learning time-series processing often relies on convolutional neural networks with overlapping windows. This overlap allows the network to produce an output faster than the window length. However, it introduces additional computations. This work explores the potential to optimize computational efficiency during inference by exploiting convolution's shift-invariance properties to skip the calculation of layer activations between successive overlapping windows. Although convolutions are shift-invariant, zero-padding and pooling operations, widely used in such networks, are not and complicate efficient streaming inference. We introduce StreamiNNC, a strategy to deploy Convolutional Neural Networks for online streaming inference. We explore the adverse effects of zero padding and pooling on the accuracy of streaming inference, deriving theoretical error upper bounds for pooling during streaming. We address these limitations by proposing signal padding and pooling alignment and provide guidelines for designing and deploying models for StreamiNNC. We validate our method in simulated data and on three real-world biomedical signal processing applications. StreamiNNC achieves a low deviation between streaming output and normal inference for all three networks (2.03 - 3.55% NRMSE). This work demonstrates that it is possible to linearly speed up the inference of streaming CNNs processing overlapping windows, negating the additional computation typically incurred by overlapping windows.

E-textiles are rapidly emerging as an important area of electronic circuit applications. It also facilitates many socially important applications such as personalized health, elderly care, and smart agriculture. However, the environmental impact and sustainability of e-textiles remain very problematic. STELEC, short for Sustainable Textile ELECtronics, is an interdisciplinary research project funded by the European Innovation Council (EIC) under the Pathfinder programme on the responsible elec-tronics topic seeking cutting-edge innovation. STELEC started in September 2024 and is in its initial stage. The project is a multinational collaboration of research institutes, universities and companies across Europe. It aims at developing next-generation textile-based electronics in applications from sensing, processing to AI, with a commitment to full lifecycle sustainability.

Designing AI-based applications personalized to each user's behavior presents significant challenges due to the cold start problem and the impracticality of extensive individual data labeling. These challenges are further compounded when deploying such applications at the edge, where limited computing resources constrain the design space. This paper introduces a novel approach to AI-driven personalized solutions in biosensing applications by combining deep learning with clustering-based separation techniques. The proposed Clustering and Learning for Emotion Adaptive Recognition (CLEAR) methodology strikes a balance between population-wide models and fully personalized systems by leveraging data-driven clustering. CLEAR demonstrates its effectiveness in emotion recognition tasks, and its integration with fine-tuning enables efficient deployment on edge devices, ensuring data privacy and real-time detection when new users are introduced to the system. We conducted experiments for model personalization on two edge computing platforms: the Coral Edge TPU Dev Board and the Raspberry Pi with an Intel Movidius Neural Compute Stick 2. The results show that initial cluster assignment for new users can be achieved without labeled data, directly addressing the cold-start problem. Compared to baseline validation without clustering, this proposal improves accuracy metric from 75% to 81.9%. Furthermore, fine-tuning with minimal labeled data significantly improves accuracy, achieving up to 86.34% for the fear detection task in the WEMAC dataset while remaining suitable for deployment on resource-constrained edge devices.

In this paper, we present the new FPGA EMUlation (FEMU), an open-source and configurable emulation framework for prototyping and evaluating TinyAI heterogeneous systems (HS). FEMU leverages the capability of system-on-chip (SoC)-based FPGAs to combine the under-development HS implemented in a reconfigurable hardware region (RH) for quick prototyping with a software environment running under a standard operating system in a control software region (CS) for supervision and communication. To evaluate our approach, we built the X-HEEP FPGA EMUlation (X-HEEP-FEMU) platform by instantiating the proposed framework with real-world hardware and software components. X-HEEP-FEMU is deployed on the Xilinx Zynq-7020 SoC and integrates the eXtendible Heterogeneous Energy Efficient Platform (X-HEEP) host in the RH, a Linux-based Python environment on the ARM Cortex-A9 CS, and energy models derived from a TSMC 65 nm CMOS silicon implementation of X-HEEP, called HEEPocrates.

In wearable sensors, energy efficiency is crucial, particularly during phases where devices are not processing, but rather acquiring biosignals for subsequent analysis. This study focuses on improving the power consumption of wearables during these acquisition phases, a critical but often overlooked aspect that substantially affects overall device energy consumption, especially in low-duty-cycle applications. Our approach optimizes power consumption by leveraging application-specific requirements (e.g., required signal profile), platform characteristics (e.g., transition-time overhead for the clock generators and power-gating capabilities), and analog biosignal front-end specifications (e.g., ADC buffer sizes). We refine the strategy for switching between low-power idle and active states for the storage of acquired data, introducing a novel method to select optimal frequencies for these states. Based on several case studies on an ultra-low power platform and different biomedical applications, our optimization methodology achieves substantial energy savings. For example, in a 12-lead heartbeat classification task, our method reduces total energy consumption by up to 58% compared to state-of-the-art methods. This research provides a theoretical basis for frequency optimization and practical insights, including characterizing the platform's power and overheads for optimization purposes. Our findings significantly improve energy efficiency during the acquisition phase of wearable devices, thus extending their operational lifespan.

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is compiled onto the platform. State-of-the-Art (SoA) compilation techniques utilize modulo scheduling to minimize the Iteration Interval (II) and use graph algorithms like Max-Clique Enumeration to address mapping challenges. Our work approaches the mapping problem through a satisfiability (SAT) formulation. We introduce the Kernel Mobility Schedule (KMS), an ad hoc schedule used with the Data Flow Graph and CGRA architectural information to generate Boolean statements that, when satisfied, yield a valid mapping. Experimental results demonstrate SAT-MapIt outperforming SoA alternatives in almost 50% of explored benchmarks. Additionally, we evaluated the mapping results in a synthesizable CGRA design and emphasized the runtime metrics trends, i.e., energy efficiency and latency, across different CILs and CGRA sizes. We show that a hardware-agnostic analysis performed on compiler-level metrics can optimally prune the architectural design space, while still retaining Pareto-optimal configurations. Moreover, by exploring how implementation details impact cost and performance on real hardware, we highlight the importance of holistic software-to-hardware mapping flows, as the one presented herein.

In this work, we propose an open-hardware low-power coarse-grained reconfigurable array connected to a lightweight microcontroller and enclosed in an application mapping framework. The latter provides complete support to configure kernels in the reconfigurable array, execute applications, and measure performance.

X-HEEP (eXtendable Heterogeneous Energy-Efficient Platform) is an open-source1, configurable, and extensible single-core RISC-V microcontroller developed at the Embedded Systems Laboratory (ESL) of EPFL for edge-computing platforms. X-HEEP can be used standalone as a low-cost microcontroller, or it can be integrated into existing platforms to act like a peripheral subsystem, or it can be extended and customized with external peripherals and accelerators nimbly. The latter is particularly appealing for novel accelerators, memories, or peripherals designers who desire a simple controller to drive their IP and communicate with the external world using software functions. X-HEEP is built on top of existing, mature open-source IPs such as CPUs, peripherals, and many other building blocks from the OpenHW Group, the PULP team from ETH Zurich and the University of Bologna, and lowRISC. Its contribution includes its expandability, configurability, and agile use, targetting a large number of users to take one step further towards the democratization of open-source hardware.

This paper addresses the optimization of embedded platforms to meet the computing and real-time requirements of cyber-physical systems and IoT applications, including embedded intelligence. In this context, schedulers are vital in enhancing processor utilization in industrial contexts. Although existing research has focused primarily on the schedulability of periodic tasks, event-driven tasks better represent these new embedded intelligence scenarios in the real world. This work explores static and dynamic scheduling policies within a general scenario and a specific case study based on an actual industrial application. The proposed dynamic scheduler has been integrated into the FreeRTOS kernel and has been employed to conduct all of our experiments on industrial products within the smart home domain. Our results show that, while we can respect real-time requirements, our proposed dynamic scheduling can improve the performance of event-driven applications by reducing missed task deadlines by up to 60 %. Moreover, we have also developed a lightweight version of our dynamic scheduler for industrial products that reduces average timing overhead for task selection and insertion by up to 34.7 % and memory overhead for task creation and list scheduling by up to 74.7 % compared to state-of-the-art static alternatives.

Wearable technology is having a profound impact in healthcare applications. In this context, one of the main goals of current wearable systems is to provide new devices capable of delivering a greater amount of more precise information. Amongst the different applications, physiological continuous monitoring is becoming one of the most wanted features. In fact, most of the commercially and research grade wearable systems include cardiac activity acquisition, which is generally performed by means of photoplethysmography sensors (PPG). These optical-based sensors present different challenges related to the prevailing of a good signal quality. Thus, in case of dealing with digital processing algorithms which are responsible for extracting different features from such signal, this fact can lead to erroneous results. On this basis, this paper presents an ongoing work towards the design of an interval type-II fuzzy-based system for the PPG signal quality assessment. Moreover, this initial proposed system is implemented into a constrained 32-bit ARM Cortex-M4 system-on-chip. Specifically, the system uses a reduced set of features together with a low complexity fuzzy rule base Mamdani inference model, and is based on a non-overlapping 3-second signal processing window. Results show that the system achieved overall accuracy of 94.84%. The proposed system has great potential for integrating accurate and reliable continuous health monitoring systems into constrained edge devices.

The main research motivation of this article is the fight against gender-based violence and achieving gender equality from a technological perspective. The solution proposed in this work goes beyond currently existing panic buttons, needing to be manually operated by the victims under difficult circumstances. Instead, Bindi, our end-to-end autonomous multimodal system, relies on artificial intelligence methods to automatically identify violent situations, based on detecting fear-related emotions, and trigger a protection protocol, if necessary. To this end, Bindi integrates modern state-of-the-art technologies, such as the Internet of Bodies, affective computing, and cyber–physical systems, leveraging: 1) affective Internet of Things (IoT) with auditory and physiological commercial off-the-shelf smart sensors embedded in wearable devices; 2) hierarchical multisensorial information fusion; and 3) the edge-fog-cloud IoT architecture. This solution is evaluated using our own data set named WEMAC, a very recently collected and freely available collection of data comprising the auditory and physiological responses of 47 women to several emotions elicited by using a virtual reality environment. On this basis, this work provides an analysis of multimodal late fusion strategies to combine the physiological and speech data processing pipelines to identify the best intelligence engine strategy for Bindi. In particular, the best data fusion strategy reports an overall fear classification accuracy of 63.61% for a subject-independent approach. Both a power consumption study and an audio data processing pipeline to detect violent acoustic events complement this analysis. This research is intended as an initial multimodal baseline that facilitates further work with real-life elicited fear in women.

Wireless Sensor Networks are nowadays employed in several applications. Cyber-physical systems, health-care instruments and Internet of Things are using hundreds of smart sensors, which include also processing capability together with sophisticated communication protocols. The presence of faults in these critical applications must be checked during runtime, to detect transient and permanent faults that could seriously affect the entire system dependability and endanger human users. Continuous checking has been proven as inefficient in many cases, due to the low degrees of observability and controllability and to the limited life time of batteries. Even, on-line testing is often unable to report the presence of internal errors, which can remain latent during long times. In this paper, a proposal is presented for improving the on-line testability of the different type of nodes in a WSN, saving energy and tracking error from their origin.