As the feature size of the CMOS technology keeps scaling down, the charge sharing caused by radiation is becoming more and more prominent, and the occurrence possibility of the triple-node upset (TNU) increases significantly. In this paper, we propose a low-overhead and TNU-tolerant latch (LTTL) that leverages three parallel storage cells and an output-level error interceptive module to achieve complete TNU tolerance while minimizing design overhead. The optimized structure eliminates redundant devices and employs a high-speed D-to-Q path, significantly reducing delay-area-power product (DAPP). Even any three nodes of the latch are flipped at the same time, the output of the latch can retain the original value. Simulation results not only confirm the TNU tolerance of the proposed latch but also demonstrate that the latch can provide a 57% reduction in delay, 20% reduction in area, and 62% reduction in DAPP on average compared to state-of-the-art TNU-tolerant latches.

As the interaction layer between electronic devices and the external environment, ensuring the proper functioning of analog circuits (ACs) has garnered extensive attention from both academia and industry. Compound faults, a common type of fault in ACs, are challenging to handle with existing data-driven diagnostic approaches due to the difficulties in data collection. To address this issue, this paper proposes a zero-shot diagnostic framework based on mechanism compensation-digital twin, aiming to tackle the diagnostic challenge of compound faults in ACs under data scarcity conditions. Firstly, we introduce a mechanism compensation-digital twin-based data generation scheme (MC-DT). This scheme generates standard fault data for the target circuit through the constructed twin model. Building on this, we further propose a mechanism-fused sample generation scheme to compensate for the limitations inherent in twin model modeling. By employing the MC-DT, a multi-source homogeneous domain dataset can be generated for the target circuit. Secondly, to effectively bridge the distribution gap between the generated data and real-world data, we employ a multi-source domain generalization network to learn domain invariant representations from the generated data, thereby enhancing the model's performance in practical application scenarios. Through case studies conducted on existing ACs using a constructed test platform, the experimental results demonstrate that the proposed scheme achieves accuracies of 71.63%, 77.49%, and 74.64% in three different zero-shot diagnostic tasks, respectively, exhibiting significant advantages over advanced zero-shot methods.

Building an interpretable fault detection and diagnostic model based on few-shot circuit samples and prior information about circuit structures is of significant importance. To fill these gaps, we propose a graph-based multitask transfer learning (TL) method for fault detection and diagnosis of circuits under few-shot conditions. First, in order to model the interconnections of nodes in a circuit, the sample data is organized into a graph structure, and a semi-supervised graph-based structural feature fusion method is proposed. The proposed method can accept graph-structured data and process the data using feature fusion methods. Second, to improve the model performance under few-shot conditions, two TL mechanisms are proposed for the topological structure characteristics of analog circuits as well as circuit signal characteristics. Finally, through a parameter-shared strategy, we propose a task transfer-based fault diagnosis approach. Experimental results on three different circuits show that the proposed method has the best diagnostic accuracy compared to typical detection and diagnosis schemes.

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this paper, we propose a novel latch, namely MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

With the rapid advancement of CMOS technologies, integrated circuits are becoming more prone to soft errors, e.g., triple-node upsets (TNUs). In this paper, to effectively tolerate TNUs, an input-split C-element-based DICEs (IC-DICEs) based TNU-recovery latch is proposed. The latch employs three interlocked IC-DICEs to allow recovering from any TNU. Simulations demonstrate the TNU recovery of the latch, and also demonstrate that the proposed latch can reduce delay by 87.21%, area by 27.04%, and delay-area-power product (DAPP) by 87.44% on average, compared to the alternative latches.