Detailed routing constitutes a critical phase in the very large-scale integration (VLSI) physical design, widely regarded as the most time-consuming and computationally intensive step in the back-end design process. Due to its iterative nature and strong data dependencies, conventional parallel acceleration techniques often suffer from limited scalability and effectiveness. To address these challenges, we propose RouterAcc, an FPGA-based software–hardware co-design acceleration framework tailored for VLSI detailed routing. RouterAcc incorporates an access analysis mechanism and a termination condition strategy to accelerate convergence. Furthermore, we employ a hierarchical storage mapping scheme and a flexible dimension-partitioning architecture to alleviate memory bottlenecks and enhance data locality. Additionally, RouterAcc leverages a hierarchical comparison pipeline with fully parallelized computing units and a data preprocessing strategy to maximize computational efficiency. Experimental results on the ISPD’18 benchmarks demonstrate that RouterAcc achieves consistent speedups of 2.1×–2.3× over TritonRoute with less than 1% quality degradation. With further co-optimization, RouterAcc attains speedups of 2.7×–11.8× while maintaining routing quality comparable to TritonRoute and surpassing Dr.CU 2.0 as well as the state-of-the-art (SOTA) FPGA-based approaches.

Hyperdimensional computing (HDC) has emerged as a promising cognitive computing paradigm, offering exceptional robustness and energy efficiency for intelligent applications. However, the computational demands of HDC, particularly during the encoding and associative search phases, pose significant challenges due to their time and resource intensity. In this paper, we propose LUT-HD, a software-hardware co-design framework that accelerates HDC inference by leveraging efficient table lookup techniques. First, we introduce a binary code quantization (BCQ) algorithm based on a lookup table (LUT) that transforms costly matrix-vector multiplications in HDC into simple table lookups using precomputed results. Next, we propose a custom FPGA-based accelerator tailored for LUT-based HDC to strike a balance between accuracy and efficiency. This accelerator incorporates a performance-optimized pipeline for encoding and associative search, enhancing computational speed and resource utilization. Experimental results demonstrate that LUT-HD achieves up to 14.6 × inference speedup and reduces 97.3% energy consumption compared to the GPU platform. In addition, compared to state-of-the-art (SOTA) HDC solutions, LUT-HD offers a 5.5× speedup with negligible accuracy loss and reduces 44.8% energy consumption.

Routing is a critical and time-consuming stage in circuit physical design. The typical approach involves 2D routing followed by 3D layer assignment, with most state-of-the-art methods using sequential assignments, which limits the solution space due to the fixed order in which nets are processed. This paper proposes a two-stage layer assignment paradigm inspired by the placement process. First, we apply an analytical method to simultaneously assign layers for all nets, leveraging GPU acceleration to enhance computational efficiency. Then, a simulated annealing algorithm further optimizes the segment assignments. Experimental results show that, compared to state-of-the-art sequential and concurrent layer assignment algorithms, our method reduces via count by 16.9% and 1.5% in global routing and by 5.3% and 3.5% in detailed routing, respectively, with minimal wirelength increases. Additionally, our algorithm achieves the fewest DRC violations across all benchmarks.

Modern circuit layout centerline extraction is an essential step in estimating the parasitic inductance and verifying the layout performance in mask verification. As the continued feature size shrinking and the complexity of modern circuit design keeps growing, heterogeneous layout centerline extraction has become even more challenging. In this paper, we first formulate a Voronoi diagram-based problem transformation to collect all centerline points. Then, a graph-based initial centerline generation algorithm is presented to handle all invalid centerline points effectively. Finally, a heterogeneity-aware centerline optimization method is proposed to generate optimized design-violation-free centerline results for irregular structures. Compared with the state-of-the-art commercial 3D-RC parasitic parameter extraction tool RCExplorer and the 1st place in the 2019 EDA Elite Challenge Contest, experimental results show that our algorithm achieves the best average precision ratio of 99.7% on centerline extraction while satisfying all design constraints.

Metal fill insertion has become an essential step in reducing dielectric thickness variation and improving pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. However, it is a great challenge to consider three types of capacitances (i.e., area, fringe, and lateral capacitances) with design rules and density constraints at the fill insertion stage simultaneously. This article presents an efficient timing-aware fill insertion algorithm for minimizing the total capacitance and fill amount, considering the density constraints. First, we present an initial metal fill insertion and design-rule-aware legalization to obtain an initial fill insertion solution quickly. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to reduce the capacitance of each equivalent path globally. Third, we propose a density-aware coupling capacitance optimization method and a fast Monte Carlo-based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amount. We evaluate the performance of our algorithm on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first-place team of the contest and the state-of-the-artwork, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount in a comparable runtime.

With the continued feature-size shrinking in modern circuit designs, the layout performance estimation and parasitic import calculation based on the extracted centerline result play an important role in mask verification. Most previous works on layout centerline extraction focus on identifying the connectivity among the devices in a mask layout, with few ones collecting accurate centerline information for mask verification while considering design constraints. In this paper, we first formulate the centerline extraction problem as a Voronoi diagram to collect centerline points. Then, we present a graph-based invalid centerline removal algorithm to generate an initial centerline result. Finally, a complexity-driven centerline optimization method is proposed to further optimize the centerline while considering design constraints. Compared with the commercial 3D-RC parasitic parameter extraction tool RCExplorer and the 1st place in the 2019 EDA Elite Challenge Contest, experimental results show that our algorithm achieves the highest average precision ratio of 99.8% on centerline extraction while satisfying all design constraints in the shortest runtime.