The conventional D-type flip-flop (DFF) is sensitive to the particle induced Single Event Upsets (SEUs). Thus, the radiation tolerance improvements for flip-flops by using novel layouts have attracted considerable interests in space application. In this paper, the SEU hardened fishbone layouts are proposed and employed to the delay module and slave latch cells in our test chip, and the width of radiation induced transient pulses is analyzed by our detailed characterizations. The actual radiation sensitivities of the new layouts are also evaluated by our systematic heavy ion experiments. Without additional consumption of transistors for the basic Double Interlocked Storage Cell (DICE), the obvious enhancements of SEU tolerance for the fishbone layouts are verified under static tests, though the initial clock signal has significant influence on SEU cross sections. The consistent SEU mitigation results of the employed fishbone layout for both the delay module and flip-flop cell indicate that the novel structure may be suitable for harsh radiation environment.

The advanced FDSOI technology has improved performance and inherent SEU resistance of integrated circuits, which is beneficial to the space applications. This paper provides the comprehensive characterization of SEU sensitivities based on the 3D-TCAD and SPICE simulations, as well as the irradiation results. We concentrate on the transient pulse, charge sharing, and collection effects of FDSOI circuits. The impact of strike location on transient features is evaluated in simulation, and the influence of charge sharing effects on SEU thresholds of SRAM is also analyzed. The SEU sensitive regions are characterized, which are closely related to the internal bipolar amplification effect and affected by the strike location. Additionally, the charge sharing effects are analyzed and verified by the combination of our circuit-level simulations and irradiation experiments based on the 256 Kbit pulse-mitigated SRAM. The split charge injection simulations show that the SEU threshold reduces about ~97% for the worst condition. Whereas, the actual SEU threshold of the pulse-mitigated FDSOI SRAM is not very small due to the limited charges shared by adjacent cells. The results provide a meaningful guidance for the radiation hardening design of FDSOI integrated circuits.

Image inpainting algorithms based on the deep learning are rapidly developed in the past few years, as they can synthesize textures and structures while maintaining semantic continuity. However, due to the limitations of existing loss functions and convolution, the generated images are usually blurry and have artificial textures. In this paper, a real-time image inpainting system using PatchMatch based two-generator adversarial network (PatchMatch-GAN), is proposed to improve the clarity of generated images. The first generator is committed to continuous semantic textures, and the second one focuses on the image sharpness. Parallel-dilated convolution is used to enlarge the receptive field of filters. For the first generator, a pre-trained VGG16 is used as an encoder to extract features. For the second generator, a DCGAN-like network is designed to generate images. And a feature replacement method is utilized to improve the resolution. The edge loss has also been proposed as a part of the loss function to emphasize the role of the shape of objects. Experiments are carried out on place2 and irregular mask datasets. Compared with GLGAN and CAGAN, in PSNR, the improvements of our system are 3.33% and 2.7%, respectively; in FID, the improvements of our system are 59.54% and 35.59%, respectively. Moreover, the average processing time of the whole system is 29.96 ms, which is 6.56 times faster than GLGAN, and 21.33 times faster than CAGAN. These show that our system can achieve better image inpainting results while meeting the requirements of real-time processing speed.