A hybrid sigma converter integrated with a digital low dropout (DLDO) regulator is presented in this paper and designed for high-density power delivery applications. The proposed converter employs an input-series and output-parallel (ISOP) topology, combining a high-side hybrid converter for high power efficiency and a low-side DLDO for rapid transient regulation. An auxiliary control loop minimizes the DLDO’s dropout voltage across wide input and output voltage ranges, eliminating efficiency degradation under non-optimal operating conditions. The converter achieves a peak efficiency of 92%, with a system power density of $101.3 \mathrm{~W} / \mathrm{cm}^{3}$. A $1.6 \mu$ s response time and $\mathbf{3 6 m V}$ voltage droop are achieved with a $\mathbf{2 A}$ load transient.

This paper presents a power-efficient error-feedback and cascaded-integrator-feedforward (EF-CIFF) hybrid noise-shaping (NS) successive approximation register analog-to-digital converter (SAR ADC). A joint dynamic amplifier, comparator and lossless passive summer structure is proposed in the NS SAR ADC, where a pair of capacitors is reused among the above three sub circuits. The capacitors are first employed as the load of the dynamic amplifier, then used to store the residual signal in the summer, and finally used to compose a dynamic-biased comparator. The joint structure and the fully dynamic operations make the NS SAR ADC power-efficient. The ADC is designed in a 40nm CMOS. With a sampling rate of 50MHz, the ADC achieves 81.8dB SNDR over a 3.125MHz BW in simulation. The power consumption is 190.3μW, resulting in a Schreier FoM of 184.0dB.

This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power consumption, transistor size, and offset, a reconfigurable reference-embedded comparator is proposed. The comparator is first configured with 7 embedded reference voltages, which can complete the conversion of 3 bits in one cycle. The 3-bit/cycle comparator is then reconfigured to 1-bit/cycle in the last conversion cycle, with improved noise performance and reduced the offset mismatches between the seven latches. As a result, the ADC achieves relatively good precision with considerable power efficiency. A design example of 1-GS/s 7-bit SAR ADC in 40nm CMOS technology is presented. Simulation results show that the ADC achieves a spurious free-dynamic-range (SFDR) of 53.98 dB a signal-to-noise-and distortion ratio (SNDR) of 42.51 dB, with a figure-of-merit of 27.3 fJ/conv.-step.

This paper presents a 7.68MSps 20kHz-BW nested continuous-time (CT) delta-sigma modulator (DSM) analog-to-digital converter (ADC). The nested DSM is composed of an inner analog CT DSM and a weighted multi-threshold MSB-pass quantization path. In the inner analog CT DSM, a negative-R-based cross-RC integrator structure is employed to reduce the resistance by 8×, thus improving area efficiency and alleviating parasitic issues introduced by large standard poly resistors. In the MSB-pass quantization path, several techniques including weighted counting, multi-threshold MSB-pass comparison, look-ahead comparison, and consecutive identical state detection are proposed. These techniques help to double the speed of the proposed nested DSM over the conventional nested DSM. Fabricated in a 180nm CMOS, the prototype DSM achieves SNR/SNDR/SFDR of 108.3dB/107.3dB/121.6dBc, with maximum resistance of only 179kΩ in the loop filter. The measured Schreier figure of merit (FoMS) is 183.6dB.

The Ising machine is regarded as a promising computing architecture for obtaining approximate solutions to some nondeterministic polynomial time hard (NP-hard) problems. Utilizing a CMOS process, a large-scale Ising machine can be integrated to achieve enhanced energy efficiency compared to classical computing approaches. This work presents a fully symmetric, oscillator-based CMOS Ising machine architecture, which employs differential ring oscillator (ROSC) to implement spin, ensuring consistency between the theoretical framework and practical implementation. The coupled ROSC array is mathematically proven to have a Hamiltonian in the form of the Ising model, making it particularly suitable for implementing the Ising machine. A 240-spin CMOS Ising machine has been fabricated and tested. The proposed Ising machine takes a square lattice topology with four-level, reconfigurable coupling parameters with sign. Using a successive approximation sampling scheme, the Hamiltonian can be refined with the increasing iterations. The prototype demonstrates a power consumption of 26.3$\mathrm {\mu \text {W} }$/Spin, indicating significant energy efficiency and performance enhancement.

This paper presents a 4th-order continuous-time$\Delta \Sigma $modulator (CTDSM) employing a 6-bit time-domain quantizer. The implemented quantizer employs a time-to-digital converter (TDC)-based architecture which strikes a good balance among speed, resolution and power efficiency. A novel background calibration technique is proposed to mitigate dynamic inter-symbol interference (ISI) errors in multi-bit digital-to-analog converters (DACs) while introducing negligible additional excess loop delay (ELD), power consumption and circuit complexity. The prototype in a 40-nm CMOS is sampled at 630 MHz, achieving an SNDR/SNR/SFDR/DR of 75 dB / 77.9 dB / 86.6 dBc / 81 dB over a signal bandwidth of 25 MHz. The proposed background ISI error calibration scheme suppresses 2nd- and 4th-order harmonics by 8.5 dB and 3.5 dB, respectively. The total power consumption is 21.23 mW, achieving a Schreier Figure of Merit (FoMs) of 171.7 dB.

The sampling noise cancellation (SNC) technique has been applied to noise-shaping SAR (NS-SAR) ADCs to reduce the sampling capacitance, which makes the ADCs more easy-driven. However, the traditional SNC technique limited its applications by the PVT-sensitive noise cancellation ratio and hence noise performance. This paper proposes a new SNC technique with self-calibrated PVT-robust noise-cancellation ratio. The error of the noise-cancellation ratio (NCR) is detected and calibrated in background without any external dither or test signal. Simulation results show that the proposed SNC technique achieves more PVT-stable NCR over a traditional SNC scheme.

This article presents an energy-efficient single-ended transceiver featuring the proposed AC/DC-coupled pre-emphasis feed-forward equalizer (PE-FFE) and edge-dependent phase-modulation decision feedback equalizer (PM-DFE) for low-power memory controllers. Specifically: 1) on the transmitter (Tx) side, an AC/DC-coupled PE-FFE is implemented in a ground-terminated Tx to minimize the equalization (EQ) power and maximize the output swing; 2) on the receiver (Rx) side, an edge-dependent PM-DFE operating on the full-swing signal edges is proposed for time-domain EQ, which improves sampling margin and reduces the linear EQ requirement as well as the power consumption. The design, fabricated in 22-nm CMOS, achieves a data rate of 20 Gb/s/pin with a 41 mV increase in the Tx output eye height and a 0.12 UI increase in the Rx sampling margin over a channel with a 10.3 dB loss. Measurement results reveal an energy efficiency of 0.45 pJ/b and 0.38 pJ/b for the Tx and the Rx, respectively, and a figure-of-merit of 0.081 pJ/b/dB (Tx+Rx).

This paper proposes a look-up-table (LUT)-based background calibration to improve the linearity of the ring voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC). The nonlinearity of the tuning gain$(\boldsymbol{K}_{\mathbf{VCO}})$of the VCO is considered as that there is an individual$\boldsymbol{K}_{\mathbf{VCO}}(\boldsymbol{K}_{\mathbf{VCOI}})$for each ADC output level. The$\boldsymbol{K}_{\mathbf{VCO}}-\mathbf{Locked}-\mathbf{Loop}$(KLL) is employed to force the$\boldsymbol{K}_{\mathbf{VCOI}}\mathbf{s}$to the same reference value, thus eliminating the nonlinearity. The effectiveness of the KLL-assisted linearization scheme is not affected by the matching property of the technology and the characteristics of ADC input signal. Thanks to the KLL-assisted calibration, the total harmonic distortion is suppressed by 37.8dB with the required ADC output samples of 218, achieving a fast linearization process.

This paper presents a 3bit/cycle 1GS/s8-bit SAR ADC with asynchronous ping-pong quantization scheme. With the proposed scheme, settling requirement of the reference voltages for multibit quantizer can be relaxed. In addition, loop-unrolled technique can be easily embedded in the SAR logic for higher speed without extra hardware consumption. Moreover, using the ping-pong scheme, the comparator offset can be corrected in background mode without extra calibration phase. The ADC is designed and simulated in 22nm CMOS process. Without calibration, the ADC achieves 33.4 dB SNDR. With offset calibration, the SNDR can be improved to 47.2 dB.

This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of$0\sim 80~^{\circ }\text{C}$and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.

This paper presents a phase domain excess loop delay compensation (ELDC) technique for voltage-controlled oscillator-based (VCO-based) continuous time (CT) ΔΣ ADC. The ELDC is achieved by shifting the phase of the sampling clock which composes a zero-order feedback loop in phase domain and avoid long latency between quantizer and DAC. The phase shifting is realized by a phase selector which selects the sampling clock from multi-phase clock signals generated by the phase interpolator. To ensure the stability of the ΔΣ ADC, a two-step phase selector is proposed to optimize the latency in the zero-order feedback loop. Simulation results shows that the proposed technique can effectively compensate ELD in phase domain and low latency feature in the feedback loop makes the technique suitable for high speed VCO-based CT ΔΣ ADC.

Dynamic amplifiers are favored for the low power consumption feature in applications such as residual amplification, but the temperature-dependent gain variation limits their performance. In this paper, a temperature-compensated common-mode voltage detector is proposed for dynamic amplifiers to maintain performance against temperature variation. The proposed method employs a power-saving negative temperature coefficient reference voltage generator, a switched-capacitor subtractor and a temperature-insensitive inverter based zero-crossing detector to alleviate gain variation. Simulation results show that the proposed method reduces the maximum gain variation from 16.0% to 2.2% in a wide temperature range from -40°C to 125 °C with a frequency-dependent power consumption of only 16.0uW at 250MHz in 40nm CMOS technology.