Xumeng Zhang

dblp:258/3766 · DBLP profile ↗
← Back
6ranked-venue papers
0as first author
6since 2021 · last 2026
0000-0002-3828-151XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 An RRAM-based Neuromorphic Sleep Monitoring System for Energy-efficient Edge Healthcare Applications
Fangduo Zhu, Jingsong Zhang, Jinhao Liang, Xumeng Zhang, Qi Liu 0010
ISCAS8
2026 An RRAM-based Multi-Timescale Spiking Processor with Reconfigurable Neurons
Jinhao Liang, Fangduo Zhu, Siyuan Ouyang, Jingsong Zhang, Xumeng Zhang, Qi Liu 0010, Ming Liu 0022
ISCAS7
2026 A Pipelined NoC-Based Membrane Shortcut SNN Architecture for Low-Latency Spike Sorting
Jingsong Zhang, Fangduo Zhu, Siyuan Ouyang, Jinhao Liang, Xumeng Zhang, Qi Liu 0010
ISCAS8
2026 CogECI: Context Grounded Document-level Event Causality Identification via Large Language Models
Zefan Zhang, Xumeng Zhang, Shijie Jiang, Tian Bai 0002
Knowl. Based Syst.2
2025 SDISC: A Spike-Driven Human-Machine Interface with In-Situ Computing for Real-Time Low-Power Interaction
abstract
Feature extraction and classification of bio-signals are crucial in human-machine interface (HMI), yet suffer from high delay and limited energy efficiency using conventional hardware. To mitigate this challenge, we propose an SDISC architecture, a neuromorphic HMI with the innovation from signal encoding, computing-in-memory (CIM) hardware, to algorithm-hardware co-optimization. The following strategies are implemented: (1) A spike-driven feature extractor, achieving > $10 \times$ sparser dataflow than frame-based method; (2) In-situ computing based on resistive random-access memory (RRAM), enabling energy-efficient (4.09 TOPS/W) spiking neural network (SNN) classifier; (3) A Spike-Activity-Distillation algorithm and an Aid-Loser-Only recovery scheme to alleviate the non-ideality of RRAM devices, ensuring SDISC maintains high accuracy ($\sim \mathbf{9 8. 0 \%}$) in long time inference ($\boldsymbol{\gt} \mathbf{1 5}$ days). We further develop an end-to-end SDISC system for real-time EMG-based robot control, achieving a low latency ($34 \mu \mathrm{~s}$) and low power ($39.72 \mu \mathrm{~W} /$ sample) interaction on edge.
Fangduo Zhu, Jingsong Zhang, Xumeng Zhang, Siyuan Ouyang, Chenyang, Hao Jiang 0024, Qi Liu 0010
DAC4
2022 A neuromorphic core based on threshold switching memristor with asynchronous address event representation circuits
Jinsong Wei, Xumeng Zhang, Zuheng Wu, Mansun Chan, Qi Liu 0010, Hong Chen 0002
Sci. China Inf. Sci.3