Orthogonal frequency-division multiplexing (OFDM) is widely used in modern wireless, telecommunications, and broadcasting standards due to its multipath tolerance and high spectral efficiency. It enables high-data-rate transmission while mitigating inter-symbol interference by extending symbol duration. Many OFDM system designs have been developed, but most of them have put a halt on MATLAB simulation or register-transfer level (RTL) implementation only, lacking real-time testing and TCP/IP integration -- a feature that is needed in many wireless communication devices nowadays. This paper presents a full design integration and implementation of an OFDM transceiver system on the ADRV9361-Z7035 Software-Defined Radio (SDR) FPGA development board, which integrates the AD9361 RF Agile Transceiver with the Xilinx Z7035 Zynq-7000 SoC. The design process includes creating MATLAB models for each OFDM block, developing system objects for data transmission, and verifying the system using an SDR MATLAB model. The implementation involves constructing an RTL model and developing Linux kernel drivers for local processing, independent of MATLAB and Simulink. Transmitter power performance measurements across various modulation and coding schemes indicate optimal performance within the 700 MHz to 900 MHz range, with a maximum power of 13.6 dBm using BPSK FEC 1/2. Receiver sensitivity measurements show that most modulation and coding schemes (MCS) have met their standard sensitivity levels. Throughput performances for each MCS were compared to theoretical values and benchmarked against the Silvus Streamcaster 4200, highlighting strong performance across the MCS, with minor areas for improvement in 16-QAM configurations. The integrated OFDM system has been able to be used for multimedia applications, such as local video streaming and internet browsing.

Optical wireless communication (OWC) has been considered a promising solution for overcoming the spectrum limitations of RF in wireless communication. However, studies on OWC systems, particularly on actual real-time prototyping, are limited and only focus on simulation and experiments using waveform generators and oscilloscopes. Meanwhile, the data rate requirements for optical communication systems are rapidly increasing, approaching the Gbps range. Therefore, the development of real-time prototypes with high data speeds is essential and requires super sample rates (SSR), necessitating signal processing blocks capable of processing multiple samples in parallel within a single clock cycle while operating at very high clock frequencies. To address these requirements, this work proposes a parallel implementation of an orthogonal frequency division multiplexing (OFDM) baseband processor on an FPGA for OWC systems. The proposed system operates with a bandwidth of 320 MHz, achieving a maximum raw data rate of 720 Mbps at 16-QAM 3/4 modulation. This performance is comparable to that of the IEEE 802.11be WiFi 7 standard. The proposed system is applicable not only to underwater OWC but also for indoor OWC (e.g. Li-Fi), broadening its potential use cases in next-generation wireless communication networks.

Light Fidelity (Li-Fi) is the complementary technology to the RF based communication in 6G. It uses optical spectrum which is completely free and unregulated. Sampling frequency offset (SFO) is an issue related to the mismatch between TX and RX clock oscillators. However, this issue is often assumed to be ideal in many Li-Fi research. In this work, we aim to address this issue by proposing an FPGA implementation of SFO compensator module for OFDM system. We optimize an SFO compensation method so that it can be implemented in FPGA efficiently in terms of resource usage. We evaluate the module by integrating it with the OFDM processor, Linux TCP/IP stack, and tested with TCP data. Real-time experiment results demonstrate that with our SFO compensator, the EVM of our Li-Fi system can be decreased up to 6.7% and 1.4% for QPSK and 16-QAM, respectively. Frame lost is decreased by 22.42% and TCP data rate is increased by 8.25x.

This article proposes a scalable accelerator for deep learning (DL) implementation on edge computing, which is often limited by power, storage, and computation speed. The accelerator is based on systolic array cores with 126 processing elements (PEs) and optimized for YOLOv3-Tiny with$448\times448$input images. Two multicast (MC) network architectures, feature map multicasting and weight multicasting, are introduced to control data stream distribution within the multicores. Results show that the proposed weight multicast (W-MC) systems outperformed the feature map multicast (FMAP-MC) systems in multicore scenarios, with up to$2.23\times $frame rates per second (FPS). The 4-core W-MC system achieved the best efficiency with an overall frame rate of 13.73 FPS/W and an overall throughput of 35.83 GOPS/W. The 8-core W-MC system delivered the best performance, with a frame rate of 38.50 FPS after normalization to the standard YOLOv3-Tiny network. The proposed accelerator offers better computational efficiency and greater accelerator utilization in real-world inference scenarios, compared to previous state-of-the-art works.