Modern integrated circuits (ICs) contain thousands of instruments to enable testing, tuning, monitoring, and so on. These on-chip instruments must be accessed through the ICs' life-time. However, when ICs are mounted on Printed Circuit Boards (PCBs), access from system-level is challenged due to complex system hierarchies with a multitude of interfaces. In this paper we enable access from system-level to chip-level instruments by proposing hardware, protocol, and communication schemes. We have validated our scheme by implementing a system with two ICs on a Field-Programmable Gate Array (FPGA) where each IC includes an IEEE Std. 1687 network, communication between ICs is with Serial Peripheral Interface (SPI) and communication with the outside is with Universal Asynchronous Receiver Transmitter (UART). In experiments we evaluate communication based on software (polling) and hardware (interrupt) as well as overhead in terms of transported data and needed area.

Reconfigurable scan networks (RSNs), like IEEE Std. 1687 networks, offer flexible and scalable access to embedded (on-chip) instruments. These networks are typically accessed from the outside via a dedicated test port, like the test access port (TAP) of IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, the IEEE Std. P1687.1 working group is exploring how existing functional ports can be used. Fundamental challenges are to determine what hardware to include in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We have previously shown hardware and protocol to access a limited type of IEEE Std. 1687 networks, known as flat segment insertion bit (SIB)-based networks. In this paper, we present a solution to handle general IEEE Std. 1687 networks. We have made a number of implementations with various benchmarks on an FPGA to evaluate the data overhead and the area usage.

Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to the fault status of a particular IC. We show how this block enables test for faulty scan chains, localization of faulty scan chains, and repair by excluding faulty scan chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.

We address access control of reconfigurable scan networks, like IEEE Std. 1687 networks. We propose an on-chip test block to perform: (1) test for faulty scan-chains, (2) localization of faulty scan-chains and (3) repair by excluding faulty scan-chains, and an access control block to (1) control so scan-chains (instruments) are only accessed in allowed combinations, (2) detection of access attempts to instrument in not allowed combinations, and (3) monitoring how theses attempts are made. The key features are two-fold. First, in respect to operation and maintenance. If the physical implementation of an IEEE Std. 1687 network changes due to faults, the instrument connectivity language (ICL) and procedural description language (PDL) need to be updated. To avoid keeping track and updating ICL and PDL for each individual integrated circuit (IC), proposed test block, placed at each IC, makes adjustments of PDL according to the faults of the particular IC. Second, a centralized access control block with key information about the network to detect and handle unauthorized access.

The IEEE Std. P1687.1 working group is currently exploring alternatives to IEEE Std. 1149.1 test access port (TAP) as the interface between the boundary of integrated circuits (ICs) and IEEE Std. 1687 networks. In this paper, we investigate the use of universal asynchronous receiver-transmitter (UART) to access IEEE Std. 1687 networks. We have developed a protocol to describe the information transported over UART and a hardware component to translate (retarget) information between UART and IEEE Std. 1687. The objective is to minimize the amount of information transported over UART and the area of the hardware component while maintaining the flexibility to access an arbitrary combination of instrument in the IEEE Std. 1687 network. We have developed software for the protocol translation, implemented the hardware component and IEEE Std. 1687 networks of different sizes in an field-programmable gate array (FPGA). For comparison, we developed a number of alternatives, all implemented on FPGA. The experimental results show that proposed scheme gives low overhead in terms of transported information (data) and low area of the hardware component.