Local defect patterns (LDP) in wafer maps are usually induced by problems in the manufacturing process. Therefore, defect pattern recognition is useful for root cause analysis, which is very important for yield optimization. Machine learning (ML) based methods can achieve good LDP recognition rate. In general, these techniques are designed to identify spatial patterns, which may not directly linked to the root cause. Besides, ML methods are more time-consuming because of the training process. In this paper, we propose to apply a rule-based method for LDP classification such that the recognized patterns are explainable. Experimental results show that the proposed method achieves roughly the same level of accuracy as other ML methods while the exaction time is much faster.

We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

The scratch defect type is difficult to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. The recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method. The method is validated by real products. Experimental results show that the average recall, precision and accuracy achieved by the proposed method are 97.22%, 98.81%, and 99.92%, respectively. Furthermore, the proposed method is based on image processing techniques alone with low processing time. In contrast to machine-learning based methods, there is no need to train a complicated prediction model.

Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.

Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a grid pattern recognition methodology taking into account both partial and hidden grid patterns. Hidden defective dies are dies in the grid contour that pass wafer test. However, such dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the potential defective dies in hidden grid patterns and mark them as faulty. As a result, the reliability of products and test cost can be significantly improved. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. A five-phase method is developed to enhance wafer maps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and also achieve 96.45% by Extremely Randomized Trees for all nine common wafer defect types averagely.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

Wafermap defect pattern detection and diagnosis provide useful clue to yield learning. However, most wafermaps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Specially, recognizing scratch and line types of defect patterns is a challenging problem for process and test engineers and it takes a lot of manpower to identify such patterns, as potential defective dies may exist on the scratch contour and become discontinuity points. However, such potential defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in potential scratch patterns and mark them as faulty. As a result, the quality and reliability of products can be significantly improved and cost of final test can be reduced. In this paper, we propose a systematic methodology to search for potential scratch/line defect types in wafers. A five-phase method is developed to enhance wafermaps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve more than 89% prediction accuracy for scratch/line types, and higher than 94% for all common wafer defect types.

We propose a machine learning based method targeted for accurate wafer defect map classification. The proposed method is referred to as TestDNA-E, as it applies ensemble learning based on improved TestDNA features. Experimental results show that the proposed method achieves high hit rate for each defect type and overall accuracy.

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

Wafer defect maps exhibit spatial failure pattern recognition for root cause analysis to improve defect diagnosis resolution and yield learning conventionally. We apply further product-driven test items to propose a wafer-level test methodology to generate a DNA-like wafer defect signature to identify wafer defects. Experience results show that our TestDNA are both effective and efficient, including the tight relation with traditional wafer defect patterns, high prediction accuracy over 90%, and improved lower non-pattern ratio from over 95% to around 11%.