Synthesized netlists often leave substantial room for area optimization due to the limited function diversity in standard cell libraries, which frequently results in recurring logic patterns that could be compacted through cell combination-referred to as hypercells in this work. While prior studies have demonstrated the potential of hypercell-based optimization, most lack efficient and scalable mining strategies. We present SOFA-H, a post-synthesis framework that extracts and remaps hypercells for maximum area reduction. SOFA-H (i) mines fanout-induced subgraphs and canonically encodes them using P-Representatives, (ii) selects an optimal set of hypercells with non-overlapping replacements via a one-shot weighted MaxSAT formulation, and (iii) supports high input, multi-output cells with scalable runtime. Evaluated on the EPFL benchmark suite synthesized using FreePDK45 and ASAP7, SOFA-H achieves average area reductions of 12.2% and 7.4%, respectively, and runs $380 \times$ faster on average at ASAP7 compared to the state-of-the-art method. These results demonstrate that the extracted hypercells offer a scalable and effective path to closing the area gap left by conventional synthesis.

Standard cell layout design at advanced technology nodes faces a massive combinatorial explosion of transistor placement possibilities, especially when targeting optimal performance, power, and area (PPA). In this work, we propose a novel framework that integrates AllSAT-based pruning and Monte Carlo Tree Search (MCTS) to tackle this challenge efficiently. Our method first employs an AllSAT formulation that incorporates routing constraints and layout heuristics to exhaustively enumerate only the legal and promising placement solutions. This dramatically reduces the solution space while preserving high-quality candidates. We then apply a guided MCTS algorithm to explore the reduced space and identify optimal or near-optimal placements under given objectives such as total wire length (TWL). Experimental results on a diverse set of standard cells demonstrate the effectiveness of our approach. The AllSAT filtering improves average solution routability from 1.1% to 62.7%, while reducing the total placement space by over 99.9%. On top of that, our MCTS achieves a 62.2× runtime speedup over brute-force exploration, with only a 0.2% degradation in TWL quality. These results confirm that our AllSAT+MCTS framework offers a scalable and practical solution for high-quality standard cell layout synthesis.

The reliability of automotive electronics is heavily affected by aging and temperature variations, which can degrade performance or cause failures. Traditional timing-prediction methods assuming a constant temperature can introduce a 17% error compared to models that incorporate temperature distribution over 30 years of aging, resulting in inaccurate reliability assessments. To address this limitation, this paper introduces the timing-prediction framework based on the Aging- and Temperature Distribution-Aware Timing Model (ATD-Timing Model) that integrates functional behaviors, aging effects, and temperature distributions for accurate analysis. By leveraging a two-phase machine-learning approach for cell-delay prediction, our ATD-Timing Model achieves an average error of 0.58% at the cell level compared to SPICE. Furthermore, after eliminating false paths at the circuit level, the average critical delay error of our timing-prediction framework is reduced to 2.22% compared to SPICE, while computational efficiency is significantly improved with an average speedup of 203.97×. This enables accurate and efficient automotive circuit reliability analysis under realistic conditions.

Cell layout generation plays a crucial role in design automation. The generated layout must not only adhere to design rules but also exhibit optimized performance in terms of factors such as delay, power, area, and cost. However, prior works often rely on metrics that fail to consider the layout-dependent effects (LDEs). Furthermore, evaluating the actual performance using commercial tools can be excessively time-consuming, especially when iteratively optimizing cell layouts. Therefore, this work proposes a new machine-learning(ML)-based ranking model to enable rapid performance ranking between layout candidates of standard cells. This model incorporates all LDEs in feature extraction, generating an ordered list of cell layouts, and evaluating only the top-Kcandidates for performance. The experiments show that this approach successfully identifies the optimal layout from ten benchmark cells, which are most used in intellectual property (IP) cores, in a sub-5 nm fin field-effect transistor (FinFET) industrial standard cell library, achieving a$348\times $speedup over the conventional flow.

To optimize power, performance, and area (PPA) of IC designs, standard cell has evolved from basic to complicated designs, resulting in complex multi-height structures. Although extensive research on single-height cell automatic synthesis, multi-height cell studies are still limited due to the extremely large solution space. In this paper, we present MAXCell, a PPA-directed standard cell layout optimization framework for both single-height and multi-height designs using anytime MaxSAT with constraint learning. This framework incorporates two novel techniques: (1) learning additional constraints from the original constraints database to accelerate convergence during problem-solving and (2) integrating a genetic algorithm with a ranking model to dynamically guide the router towards the PPA goal directly during optimization. Experimental results indicate that MAXCell outperforms previous studies that target wire length optimization, achieving a 5.5% power reduction in evaluations of 33 multi-bit flip-flop designs beyond 4nm technology. Furthermore, compared to an industrial library designed by experienced engineers, MAXCell provides a 3.5% power optimization benefit and drastically reduces the delivery time from multiple days to a mere few hours (21.6X faster). This emphasizes its efficiency and its potential in modern integrated circuit design.

Single-event-induced soft errors are serious issues in advanced nano-scale technology, causing malfunctions in systems. As the size of technology node decreases to sub-65nm with closer transistor spacing, single-event double-node upsets (SEDU) occur more frequently than single-event upsets (SEU). Previous studies handled SEDU by incorporating protection mechanisms in cell designs or modifying the physical layout. However, they have massive area overhead and SEDU cannot be fully prevented. In this paper, we propose a LESER framework to reconstruct the latch design, achieving 100% SEDU tolerance. Based on the concept of engineering change order (ECO), LESER contains a two-level analysis process to prevent SEDU with minimum modification on layout, including 1) device level and 2) circuit level. The device level extracts the current source model by TCAD simulation and the circuit level reconstructs the layout with scanning process, double-node injection test, and layout modification approach. Experiments show that the reconstructed design can achieve a 100% soft error protection rate with the costs of an increment of 6.4% in area, 1% in timing and power penalty. The results indicate that LESER can fully prevent SEDU by reconstructing the latch with minimum performance penalties.

Aging is an important determinant for the reliability of circuit designs and has been addressed by a number of protection techniques based on static timing analysis (STA). The timing reported by STA, however, is often too optimistic without considering the functional behavior of the circuit. Furthermore, signal probability has also been found to be a significant factor in the aging effect. As such, we present in this paper a timing-critical path analysis that takes function and aging into account as well as signal probability. Functional timing analysis (FTA) eliminates the false paths and generates more accurate timing. Furthermore, machine learning can be used to build models for predicting the timing of each cell for various aging lifetimes and signal probabilities. Experimental results indicate that there can be a difference of up to 6% on path delay between STA and FTA. The path ranks also differ for most of the benchmark circuits after considering aging with signal probability, resulting in the delay differences of up to 6.12 %. In conclusion, it is necessary to consider function, aging, and signal probability simultaneously when analyzing timing-critical paths in a circuit design.

A single-event double-node upset (SEDU) may appear to result in an erroneous state of the storage element due to the scalability of transistor features. Therefore, SEDU must be well addressed from the perspective of circuit reliability, especially for safety-critical electronics. Some previous studies claimed to protect against SEDUs in 65-nm process technologies, but were not thoroughly verified. To better understand the technology-scaling impact, we re-examine SEDU in different advanced technologies (including 7-nm finFET, 45-nm bulk CMOS, and 65-nm bulk CMOS). An integrated multi-level framework is developed with the current-source modeling derived from the device-level TCAD simulation, combined with voltage calculation derived from the circuit-level SPICE simulation. To adequately capture the probability of errors occurring in the latch design under all possible scenarios, this paper also considers a variety of environmental factors, such as strike angles, temperature variation, and technology nodes. Also, three classical latch designs (i.e., TMR, DICE, and HLR) have been implemented in different technologies and well calibrated for experiments. According to experiment results, it is evident that SEDU is highly dependent on both the physical layout of the design as well as its design style. DICE is found to be the most susceptible to SEDU in all three manufacturing technologies, whereas TMR and HLR can be immune to SEDU in the 45-nm and 65-nm technologies due to a lack of sufficient charge to upset more than two nodes. It is, therefore, essential to consider both the physical layout and the manufacturing technology employed for ensuring the robustness of a radiation-hardened design against particle strikes.

Design rule (DR) is the most critical challenge for generating a cell layout automatically in the advanced process technologies (e.g., finFET-EUV). Previous works explicitly encode the complicated DRs into routing constraints and automation scripts, which may not be general and efficient for addressing the DR problem. Therefore, an automatic cell layout generation (ACLG) framework is proposed and adopts three implicit-learning techniques [i.e., guidance learning (EGL), DR learning (DRL), and mistake-driven learning (MDL)], which jointly discover the knowledge of complex DRs from the existing layouts in the cell library. EGL learns the geometry behavior of the target metals from the legal cell layouts. DRL learns the DRs from layout patterns. MDL learns the routing constraints iteratively from the encountered mistakes during the layout generation (LG). These three implicit-learning techniques are combined into ACLG and developed into four core stages to cope with the DR challenge in a more general and efficient way. The experimental results demonstrate that ACLG effectively solves all the DR violations (DRVs) in an advanced finFET-EUV process (100% success rate on fixing DRVs) and successfully yields DRC-clean cell layouts for 13 benchmark cells. In addition, the proposed DRL technique is more efficient than the commercial DRC tool in excluding the illegal layout solution space. The number of iterations for a generated legal cell layout is reduced by 30% on average with DRL (3.31) compared to the commercial DRC tool (4.69). Moreover, the total runtime of generating legal layouts for 13 benchmark cells is further improved by$2.57\times $on average. Since DRL not only reduces the iterations of refining the DRVs in the generated cells but also speedups the process of DR checking (DRC) efficiently.

For the advanced process technologies (e.g, finFET with EUV), the design rules (DRs) are the most challenging issue to the generation of cell layouts and all DR violations must be solved in a legal cell layout. However, most of previous works apply explicit encoding on the selected DRs into the routing engine and cannot accommodate the rapid growth on the size and complexity of DRs as the processes continue to advance. Therefore, in this paper, we propose two implicit-learning techniques, (1) experience-guidance learning (EGL) and (2) constraint-driven learning (CDL) for effectively solving such two problems of DRs, and meanwhile develop an automatic cell-layout generation (ACLG) framework for efficiently generating legal cell layouts. The experimental results show that in a finFET-EUV process [1], EGL and CDL successfully reduce all DR violations on eight target cells where each case takes averagely three minutes. As a result, without manual effort, ACLG is capable of generating legal layouts of standard cells by implicit learning on DRs of advanced processes.

Functional timing analysis (FTA) is a renowned method of finding the true critical delay for the design under interest. By constructing conjunctive normal form (CNF) clauses based on temporal and function constraints, false paths can be identified through the satisfiability (SAT) solving. As a result, the critical delay estimated by FTA is more accurate than that by conventional static timing analysis (STA). However, FTA suffers from the extremely long formulation and computation time, as the number of the clauses in CNF grows exponentially with the increasing size of the design. Due to the reconvergent effect, thousands of clauses can be redundantly formulated for one pin. Even worse, most of them are found useless but seriously lengthen the computation time. Therefore, to avoid ineffective computation in FTA, three novel techniques are proposed: 1) encoding duplication removal (EDR) for removing duplicated functional literals; 2) redundant state propagation (RSP) for propagating temporal states to identify redundant clauses; and 3) temporal footprint identification (TFI) for combining clauses that represent constraints with the same behavior. The experiments show that under a given timing constraint, 94% clauses and 95% literals can be pruned averagely (99% clauses and 99% literals under the best case), resulting in $15.3 \times $ speedup ($72.99 \times $ under the best case) for formulation and SAT solving. As a result, the proposed techniques (EDR, RSP, and TFI) are proven effective to reduce useless computation and improve the overall performance of FTA.

As the Register Transfer Level (RTL) designs are more complicated, debugging becomes a major bottleneck in the design process. To make debugging more efficient, failure binning aims at grouping failure traces caused by the same error source together so that designers can focus on one bug at one time. However, as there are multiple bugs in a design, behaviors exhibited by failure traces are diverse and severely confuse designers. One error source may result in different appearances subject to different activation conditions. In addition, different error sources may also exhibit similar appearances among the limited number of failure traces. In this work, we propose an autoencoder-based failure binning engine name FAE for debugging RTL designs more efficiently. The autoencoders extract meaningful representations from the sparse and high-dimensional feature space to the latent space with good properties for clustering. Superior to prior works, FAE provides confidence ranks between bins and in a bin to clearly guide designers during debugging. Experimental results show that FAE can drive bins of higher purity under an acceptable number of bins than prior works, dropping only few less-informative failures. Evaluated by three common metrics for clustering, FAE also achieves averagely 13.1% improvement in purity, 25.0% improvement in NMI and 18.2% improvement in ARI, respectively. As a result, the proposed autoencoder-based engine, FAE, applies machine learning to extract useful information from diverse failure traces and is effective on failure binning with more focused debugging.