Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale integrated circuit (LSI) testing while maintaining the test quality. In this method, the performance of unmeasured LSI circuits manufactured on a wafer is statistically predicted from a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in wafer. However, actual wafers may have discontinuous variations that are systematically caused by the manufacturing environments, such as shot dependence. In this study, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into the systematic discontinuous and global components to improve the estimation accuracy. An evaluation performed using an industrial production test dataset shows that the proposed method reduces the estimation error for an entire wafer by over 33% compared to conventional methods.

Although automotive semiconductors must comply with the standard dynamic part average testing (DPAT) defined by the Automotive Electronics Council, it remains challenging to detect outliers that deviate from the spatial trend within a wafer. Outlier detection using Gaussian process (GP) regression has recently been proposed and outperformed DPAT. However, the detection performance degrades when faulty large-scale integrations are densely included in the regression. Furthermore, the applicable test items are limited because of the long computation time for regression. We propose an outlier detection method by applying ensemble learning to GP regression for simultaneously improving the detection performance and shortening the learning time. Experimental results on industrial production test data demonstrate that the proposed method improves the robustness against latent faulty chip detection by 15.6% while reducing the computation time by 98.6% compared with the conventional GP-based method.

Prefetching is an important technique for reducing the number of cache misses and improving processor performance, and thus various prefetchers have been proposed. Many prefetchers are focused on issuing prefetches sufficiently earlier than demand accesses to hide miss latency. In contrast, we propose aT-SKID prefetcher, which focuses on delaying prefetching. If a prefetcher issues prefetches for demand accesses too early, the prefetched line will be evicted before it is referenced. We found that existing prefetchers often issue such too-early prefetches, and this observation offers new opportunities to improve performance. To tackle this issue, T-SKID performs timing prediction indepen-dently of address prediction. In addition to issuing prefetches sufficiently early as existing prefetchers do, T-SKID can delay the issue of prefetches until an appropriate time if necessary. We evaluated T-SKID by simulations using SPEC CPU 2017. The result shows that T-SKID achieves a 5.6 % performance improve-ment for multi-core environment, compared to Instruction Pointer Classifier based Prefetching, which is a state-of-the-art prefetcher.

In this paper, we propose a novel method for predicting the characteristic failure rate from a small amount of data with high accuracy using the posterior distribution of the Gaussian process. In the proposed method, using multiple lots, a local pattern on the wafers is estimated from the measurement results of the target-probe test item for failure-rate prediction. For failure-rate prediction, the global trend of each wafer is predicted by the Gaussian process using WAT data and superimposed on the local pattern. The proposed method derives the failure rate of each die based on the posterior distribution using the Gaussian process in the global trend calculation. Experiments using industrial semiconductor manufacturing data demonstrate that the proposed method can reduce the estimation error by approximately 70% compared to a conventional method.

The number of patients of malignant soft tissue tumor is about 3,000 every year in Japan. In the treatment procedure of soft tissue tumor, survivability of patient must be predicted based on experience. The miss-prediction causes the unnecessary treatment or patient death, an objective decision making system based on pathological image is required. This paper proposes a convolutional neural network (CNN) based survivability and survival time prediction method using pathological image of soft tissue tumor. The proposed method trained Inception v3 and ResNetl4-based modified CNN model using 47 pathological images of 26 subjects. As the result of 4-fold cross validation test, the image-wise survivability, image-wise non-survivability, subject-wise survivability, and subject-wise non-survivability were predicted in F-measure of 0.847, 0.743, 0.909 and 0.824, respectively. Additional experiment using non-survival patients showed that the survival time was predicted in 4.57 months error.

Various techniques, such as cache replacement algorithms and prefetching, have been studied to prevent instruction cache misses from becoming a bottleneck in the processor frontend. In such studies, the goal of the design has been to reduce the number of instruction cache misses. However, owing to the increasing complexity of modern processors, the correlation between reducing instruction cache misses and reducing the number of executed cycles has become smaller than in previous cases. In this paper, we propose a new guideline for improving the performance of modern processors. In addition, we propose a method for estimating the approximate performance of a design two orders of magnitude faster than a full simulation each time the designers modify their design.

Approximate computing (AC) reduces power consumption and increases execution speed in exchange for computational accuracy. By adjusting the accuracy of approximation at runtime to reflect the optimal quality of the application, which changes constantly depending on the user’s cognitive ability and attention, AC achieves even higher efficiency. In this paper, we propose stochastic iterative approximation (SIA) that achieves dynamic and rapid control of the aggressiveness of the approximation. SIA executes a single binary code with multiple level of approximate aggressiveness that are dynamically adjusted. We propose a software implementation of SIA and hardware techniques to further improve the performance of SIA. We implement a compiler and a processor simulator for SIA as the dynamic approximation modules of RISC-V and evaluate their performance. Simulation results on six benchmarks show an adjustable trade-off between output quality and execution efficiency depending on the aggressiveness of the approximation in a single binary run.

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.