This paper addresses the speed bottleneck issue of traditional column-parallel analog-to-digital conversion circuits during the readout process of ultra-large array CMOS image sensors. A high-speed and low-power ADC based on a pipelined/time-to-digital converter hybrid architecture is proposed. This method is based on TDC technology to reduce the parasitic capacitance at the output of the MDAC circuit without compromising the conversion rate of the pipelined architecture, thus achieving a significant reduction in system power consumption. Additionally, the circuit multiplexing technology further enhances the power efficiency of the system. The proposed ADC method has been implemented and verified in a CMOS image sensor chip with an array size of 8192(H)$\times 8192$(V), manufactured with the 55 nm 1P4M CMOS process. Operating at the conditions of a clock frequency of 10 MHz and an input signal range of 1.6 V, the 13-bit ADC achieves a conversion rate of 5 MSPS, an SNDR of 73.82 dB, and an ENOB of 11.97 bits with a power consumption of$214.9~\mu $W. Compared with advanced ADCs, the proposed ADC achieves an optimal FOM1value of 0.011 pJ/step, effectively addressing the design contradiction between power consumption and conversion rate in traditional architectures. This chip achieves a row time of 200 ns and a frame rate of 610 fps with 5.23 W of power consumption.

Finding a feasible solution is the primary concern in power system dispatch. This paper studies the feasibility condition of power system dispatch under a multistage robust optimization framework considering the non-anticipativity of dispatch policy, which is difficult to be expressed via explicit constraints. The multistage robust feasible regions (MRFRs) are defined as the sets in the state space containing all points that can maintain the robust feasibility in the next period against renewable and demand uncertainties; we give a polyhedral projection condition to characterize exact MRFRs in a recursive manner, which can be regarded as an analog of Bellman’s optimality condition. However, because the multistage dispatch problem of a bulk power system has a high-dimensional state space, the computation of exact MRFRs suffers from the curse of dimensionality. We propose an inner approximation method that identifies the maximal polyhedra that are embraced by the unknown exact MRFRs; we devise a computationally efficient algorithm to retrieve the hyperplane representation of the inner approximator. Finally, we discuss how MRFRs can be used in combination with existing approaches, such as dynamic programming and rolling horizon optimization. Numerical simulations on a modified IEEE 118-bus system verify the effectiveness and advantages of the proposed methodNote to Practitioners—This paper is motivated by the problem of maintaining the feasibility in power system multistage dispatch under renewable generation uncertainty. The proposed method regards the multistage dispatch as a sequential decision-making process and recursively defines the MRFR using polyhedral projection technique, which contains all the state points in each period that can guarantee the robust feasibility in the next period. To release the curses of dimensionality, the large-scale MRFR is approximated by an inner hyper-rectangle in the state space, which can be decomposed into independent intervals of state variables, such as the generation power range of coal-fired unit and the state-of-charge range of battery storage unit. These decoupled intervals are convenient for practical use and desired in the real-world power system. At the current stage, the calculation of MRFR requires a linear model; in the future research, integers will be addressed so that more facilities such as non-ideal energy storage units and fast-startup generators can be involved.