Xinyuan Chu

dblp:259/3854 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2023
0009-0002-0773-7606ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
2 papers
Segmentation and scene understanding · 80% Trustworthy machine learning · 12% Efficient and distributed learning · 8%
Computer graphics and multimedia
1 paper
Image and video processing · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › Segmentation and scene understanding › semantic segmentation
robust semantic segmentation
0.712023
PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation · ACM Multimedia 2023
Computer vision › Segmentation and scene understanding
semantic segmentation
0.712023
PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation · ACM Multimedia 2023
Image and video processing › image restoration
image deraining
0.712023
PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation · ACM Multimedia 2023
Image and video processing
image restoration
0.712023
PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation · ACM Multimedia 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
FPGA-based CNN accelerator
0.412020
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration · FPGA 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator › low-precision arithmetic
low-precision floating point
0.412020
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration · FPGA 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.412020
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration · FPGA 2020
Machine learning › Trustworthy machine learning › robustness
adversarial robustness
0.212023
PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation · ACM Multimedia 2023
Machine learning › Efficient and distributed learning › model compression › quantization › low-precision computation
low-precision neural network
0.112020
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration · FPGA 2020

Methods — techniques the papers use, named apart from their topics

auxiliary mirror attack · 1.3adversarial training · 1.3quantization · 0.9low-precision floating point arithmetic · 0.9
YearPublicationVenuePosition
2023 PEARL: Preprocessing Enhanced Adversarial Robust Learning of Image Deraining for Semantic Segmentation
abstract
In light of the significant progress made in the development and application of semantic segmentation tasks, there has been increasing attention towards improving the robustness of segmentation models against natural degradation factors (e.g., rain streaks) or artificially attack factors (e.g., adversarial attack). Whereas, most existing methods are designed to address a single degradation factor and are tailored to specific application scenarios. In this work, we present the first attempt to improve the robustness of semantic segmentation tasks by simultaneously handling different types of degradation factors. Specifically, we introduce the Preprocessing Enhanced Adversarial Robust Learning (PEARL) framework based on the analysis of our proposed Naive Adversarial Training (NAT) framework. Our approach effectively handles both rain streaks and adversarial perturbation by transferring the robustness of the segmentation model to the image derain model. Furthermore, as opposed to the commonly used Negative Adversarial Attack (NAA), we design the Auxiliary Mirror Attack (AMA) to introduce positive information prior to the training of the PEARL framework, which improves defense capability and segmentation performance. Our extensive experiments and ablation studies based on different derain methods and segmentation models have demonstrated the significant performance improvement of PEARL with AMA in defense against various adversarial attacks and rain streaks while maintaining high generalization performance across different datasets. The source codes are available at https://github.com/JiaoXianghao/PEARL.
Xianghao Jiao, Jiaxin Gao 0001, Xinyuan Chu, Xin Fan 0001, Risheng Liu
ACM Multimedia4
2022 Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration
abstract
Low-precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs and (2) needing 16-bit floating-point or 8-bit fixed-point for a good accuracy. In this article, we propose a low-precision (8-bit) floating-point (LPFP) quantization method for FPGA-based acceleration to overcome the above limitations. Without any re-training, LPFP finds an optimal 8-bit data representation with negligible top-1/top-5 accuracy loss (within 0.5%/0.3% in our experiments, respectively, and significantly better than existing methods for deep CNNs). Furthermore, we implement one 8-bit LPFP multiplication by one 4-bit multiply-adder and one 3-bit adder, and therefore implement four 8-bit LPFP multiplications using one DSP48E1 of Xilinx Kintex-7 family or DSP48E2 of Xilinx Ultrascale/Ultrascale+ family, whereas one DSP can implement only two 8-bit fixed-point multiplications. Experiments on six typical CNNs for inference show that on average, we improve throughput by over existing FPGA accelerators. Particularly for VGG16 and YOLO, compared to six recent FPGA accelerators, we improve average throughput by 3.5 and 27.5 and average throughput per DSP by 4.1 and 5 , respectively.
Xinyuan Chu, Kun Wang 0005, Lei He 0001
ACM Trans. Reconfigurable Technol. Syst.3
2020 Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration
abstract
Low precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs, and (2) needing 16-bit floating point or 8-bit fixed point for a good accuracy.
Xinyuan Chu, Kun Wang 0005, Lei He 0001
FPGA3