Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a significant challenge to the robustness of analog integrated circuits. Existing design techniques for mitigating PVT variations involve analyzing offsets of DC operating points, but this approach often leads to compromises in circuit performance. To address this challenge, we developed a ‘PVT-Transfer’ framework to facilitate knowledge transfer with evolutionary design. Specifically, by cross-operating the circuit parameters under variations, design knowledge is transferred through parameter migration, thus enhancing the robustness of the resultant circuit. In addition, we leverage data-driven learning to discover potential similarities among PVT variations, thereby mitigating negative knowledge transfer. The PVT-Transfer Framework is evaluated on three integrated voltage references and compared with four state-of-the-art circuit sizing methods. Based on post-layout Monte-Carlo simulations, this framework is verified to offer superior performance to existing methods, yielding a 60% reduction in power consumption, an 80% increase in temperature resilience, and up to 70$\times$enhancement in the figure of merit. Further, it leads to a 60% reduction in the number of required circuit simulations and is suitable for parallel computation.

An automatic design system for the voltage reference circuit is presented in this paper. The multi-group hierarchical collaborative evolution algorithm is proposed to automatically generate the circuit structures and intelligently optimize the parameters of the circuits. In order to improve the convergence speed and reduce the optimization time, the gradient boosting decision tree (GBDT) algorithm is introduced to establish the circuit prediction model. In this paper, the automatic design of the CMOS reference source circuit is implemented in a standard 0.18μ m process. Compared with previous work, the number of iterations is reduced by 20%, the optimization time is decreased by 20.48%, the line sensitivity and temperature coefficient are improved by 65.42% and 15.47%, respectively, and the circuit power consumption is reduced by 22.50%.

A CMOS-only and multiple-output voltage reference has been proposed and simulated in a standard 0.18 μm CMOS process in this paper. Three reference voltages with their own advantages simultaneously are obtained based on the body bias technology and specific active load. Among the three references, the best temperature coefficient (TC) of 74.8ppm/°C in the range from -20°C to 80°C is obtained without using resistors and specific devices. By introducing amplifier and pushing away the main pole of the circuit, low line sensitivity (LS) of 0.06%/V and high power supply rejection ratio (PSRR) of -73dB at 10Hz are obtained without capacitor. Besides, due to the subthreshold operation, the current is as low as 77nA with a supply voltage down-to 1V.