A single-mode buck-boost converter that generates a 3.3-V power supply from a variable input voltage (${V} _{\mathbf {IN}}$) range of 2.7–4.2 V for mobile li-ion battery applications is presented. The proposed buck-boost converter employs a switched-capacitor-based buck-converter operation, in which the voltage switching operation is followed by an LC filter. This ensures continuous output current delivery and reduces conduction loss in the inductor. An efficient power-stage structure and its operation are introduced, wherein only one resistive component is connected in series with the inductor during all operation phases. The proposed buck-boost converter has been implemented in a 180-nm BCDMOS process and regulates an output voltage of 3.3 V from a${V} _{\mathbf {IN}}$range of 2.7–4.2 V by single-mode step-up/down operation. The peak efficiency of 93.4% is achieved at 2.7-V${V} _{\mathbf {IN}}$, and the peak efficiency above 90% is obtained over the entire${V} _{\mathbf {IN}}$range.

A dynamic voltage scaling (DVS) enabled distributed digital low-dropout voltage regulator (LDO) is described. The proposed distributed LDO utilizes a multi-point average sensing to enable rapid and uniform output voltage regulation across a large-scale power grid, even during unbalanced load transients. A 16-bit thermometer-code flash analog-to-digital converter (FADC) combined with unary passgate configurations and an adaptive on-resistance (R$_{\mathrm {ON}}$) modulation is employed to ensure a small output voltage ripple during DVS operation, using only a small 13.4nF output capacitor. The proposed distributed LDO has been implemented in 28nm CMOS, achieves a 10.4A/mm2 current density, 99.96% current efficiency, and a 20.1ps FOM. It has also been tested under various unbalanced load transient conditions and can rapidly regulate the output voltage back to the target level.

A typical digital low-dropout regulator (DLDO) that is clocked with a fixed frequency suffers from the trade-offs between power, speed, and stability. This paper proposes a DLDO that achieves both fast settling and low power consumption without limit-cycle oscillation (LCO) by adaptively changing the clock frequency and eventually turning off the clock in the steady state. The proposed LDO also features an inverter-based droop-compensation circuit for output-capacitor-free operation. The proposed LDO designed in a 28-nm CMOS process achieves a 70-ns settling time and a 137-mV droop voltage for the 400-mA load current transition with a 2.6-ns edge time, which translates to the figure of merit of 4.8 fs.

An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation (GDSM) is described. The proposed DLDO is mainly based on the time-driven topology while the GDSM changes the gate driving level adaptively according to the load current condition. The proposed GDSM lowers the gate driving level in the light load condition which improves the load transient response, widens the load current dynamic range, and reduces the output voltage ripple. A droop detector combined with the modulation scheme is also proposed to further improve the undershoot and recovery time. The proposed DLDO has been implemented in 28 nm CMOS and the 20,000$\times$load range is obtained even with 256 unity power switch arrays. When the load current changes from 5 mA to 85 mA, the$V_{OUT}$droop and recovery time are 130 mV and 2.5$\mu $s, which are 4.92$\times$and 70$\times$improvements compared to the baseline time-driven DLDO, respectively.

This article presents the frequency-locked high-power RF oscillator using a gallium nitride (GaN) high electron mobility transistor (HEMT) amplifier and phase-locked loop (PLL) for 2.4-GHz industrial, scientific, and medical (ISM) band applications. The proposed architecture exploits the GaN power amplifier in the positive-feedback loop, whereas the desired phase shift for the target oscillating frequency is regulated from the PLL. To the best of our knowledge, this work is the first to employ the frequency locking scheme for a high-power solid-state RF oscillator. A detailed analysis of the oscillation conditions and the efficiency is provided. The prototype circuit is implemented with hybrid phase shifters and a fractional- N frequency synthesizer. The implemented RF oscillator circuit operates from 2.3 to 2.575 GHz and achieves a low phase noise of -131.8 dBc/Hz at a 1-MHz offset frequency. The power efficiency of the proposed oscillator reaches 58%, and the PLL incurs only 0.2% efficiency degradation.