Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas Norrie
dblp:26/10565
· DBLP profile ↗
5ranked-venue papers
1as first author
3since 2021 · last 2026
0000-0002-8882-1174ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 since 2021Computer networks · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 69% Processor architecture and microarchitecture · 19% Performance modeling and evaluation · 6% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 9 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Efficient and distributed learning › distributed training › large model training
mixture-of-experts training |
1.0 | 1 | 2026 | SYMI: Efficient Mixture-of-Experts Training via Model and Optimizer State Decoupling · NSDI 2026 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 2 | 2021 | Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021 In-Datacenter Performance Analysis of a Tensor Processing Unit · ISCA 2017 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
inference accelerator |
0.5 | 1 | 2021 | Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021 |
Processor architecture and microarchitecture › instruction-level parallelism
VLIW |
0.5 | 1 | 2021 | Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021 |
Machine learning › Efficient and distributed learning › large-scale learning
large-scale model training |
0.3 | 1 | 2026 | SYMI: Efficient Mixture-of-Experts Training via Model and Optimizer State Decoupling · NSDI 2026 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › inference accelerator
neural network inference accelerator |
0.3 | 1 | 2017 | In-Datacenter Performance Analysis of a Tensor Processing Unit · ISCA 2017 |
Hardware accelerators and domain-specific architectures › tensor accelerator
tensor processing unit |
0.3 | 1 | 2017 | In-Datacenter Performance Analysis of a Tensor Processing Unit · ISCA 2017 |
Performance modeling and evaluation › benchmarking › computer architecture benchmarking
accelerator benchmarking |
0.1 | 1 | 2017 | In-Datacenter Performance Analysis of a Tensor Processing Unit · ISCA 2017 |
Performance modeling and evaluation
benchmarking |
0.1 | 1 | 2017 | In-Datacenter Performance Analysis of a Tensor Processing Unit · ISCA 2017 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | SYMI: Efficient Mixture-of-Experts Training via Model and Optimizer State Decoupling
Athinagoras Skiadopoulos, Mark Zhao, Swapnil Gandhi, Thomas Norrie, Shrijeet Mukherjee, Christoforos E. Kozyrakis |
NSDI | 4 |
| 2024 | ACF-S: An 8-Terabit / Sec SuperNIC for High-Performance Data Movement in AI & Accelerated Compute NetworksabstractRedefine networking for distributed accelerated computing to deliver peak performance, resiliency and node scale Shrijeet Mukherjee, Thomas Norrie |
HCS | 2 |
| 2021 | Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial ProductabstractGoogle deployed several TPU generations since 2015, teaching us lessons that changed our views: semi-conductor technology advances unequally; compiler compatibility trumps binary compatibility, especially for VLIW domain-specific architectures (DSA); target total cost of ownership vs initial cost; support multi-tenancy; deep neural networks (DNN) grow 1.5X annually; DNN advances evolve workloads; some inference tasks require floating point; inference DSAs need air-cooling; apps limit latency, not batch size; and backwards ML compatibility helps deploy DNNs quickly. These lessons molded TPUv4i, an inference DSA deployed since 2020. Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li 0007, Peter C. Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson 0001 |
ISCA | 11 |
| 2020 | Google's Training Chips Revealed: TPUv2 and TPUv3abstractThis article consists only of a collection of slides from the author's conference presentation. Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li 0007, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson 0001 |
Hot Chips Symposium | 1 |
| 2017 | In-Datacenter Performance Analysis of a Tensor Processing UnitabstractMany architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU. Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson 0001, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, Richard Ho 0001, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon |
ISCA | 53 |