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Alberto La Rosa

dblp:26/1345 · DBLP profile ↗
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5ranked-venue papers
4as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-authorComputer networks · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Authentication and access control · 100%
Computer networks
2 papers
Internet of things and sensor networks · 82% Physical-layer communications · 18%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Authentication and access control › user authentication
authentication and key agreement
0.512021
RIOT-AKA: cellular-like authentication over IoT devices · ICNP 2021
Internet of things and sensor networks › networked embedded systems
iot operating systems
0.112021
RIOT-AKA: cellular-like authentication over IoT devices · ICNP 2021
Reconfigurable computing and FPGAs
reconfigurable architecture
0.112005
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable processor
0.112005
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Physical-layer communications
channel coding
0.012005
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Physical-layer communications › channel coding › decoding algorithms › iterative decoding
turbo decoding
0.012005
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005

Methods — techniques the papers use, named apart from their topics

CoAP · 1.0SRAM-PUF · 0.5SRAM PUF · 0.5HTTPS · 0.5HTTP · 0.5design space exploration · 0.1hardware/software partitioning · 0.1hardware-software partitioning · 0.1
YearPublicationVenuePosition
2021 RIOT-AKA: cellular-like authentication over IoT devices
abstract
Many Internet-connected appliances are often moved to different environments, such as when they are re-located. And even when they are buried in a given physical environment, their ownership "moves", such as when a home or smart space changes hands. This calls for roaming-friendly IoT authentication devised to circumvent the need to deploy long-term authentication credentials across different visited domains. Noting that this issue has been very extensively addressed since at least three decades in cellular network, in this paper we integrate, within the RIOT IoT Operating system, an authentication and key agreement protocol designed to be as close as possible to the standard one used by 4G/5G cellular systems. Our design accounts for a few technical improvements made possible since, unlike the case of cellular networks, we are here free from back-ward compatibility issues. Our proof-of-concept implementation is built on COAP for the radio interface, and on HTTPS for the core network signaling parts, and can be further configured to use two different types of secret keys: pre-shared or on-demand, (re)generated via a SRAM-PUF API available in RIOT.
Giuseppe Bianchi 0001, Alberto La Rosa, Gabriele Restuccia
ICNP2
2005 Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform
abstract
High hardware design and mask production costs dictate the need to reuse an architectural platform for as many applications as possible. Embedded multimedia portable devices are required to perform in real time a huge variety of different algorithms, ranging from audio and image processing, to channel coding, to video games and java virtual machines. Dynamically reconfigurable architectures are an effective means to cope with both requirements. However, their effective and efficient use today is hindered by a lack of methodology and tools to extensively explore the hardware/software (HW/SW) design space, without requiring software developers to have a deep knowledge of the underlying architecture. This paper describes one such methodology, which extends the software programming model to the design flow for a reconfigurable processor. Its effectiveness is shown with the case study of a turbo decoder for universal mobile telecommunications systems, in which a remarkable 11X speed-up and 4X reduction of energy requirements with respect to a pure software implementation has been obtained, by mapping the more computation-intensive kernels to the reconfigurable hardware.
Alberto La Rosa, Luciano Lavagno, Claudio Passerone
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2004 Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
abstract
Modern embedded systems must execute a variety of high performance real-time tasks, such as audio and image compression, channel coding and encoding, etc. Reconfigurable platforms can effectively be used in these cases, because they allow to re-use the architecture for as many applications as possible. The paper describes the implementation of a UMTS turbo-decoder on one such platform, the XiRisc reconfigurable processor. Our goal is to test the development framework and design flow that we already developed on a real industrial example. Our results shows that, with some manual effort from the designer, very good performance improvements can be achieved, using a flow close to embedded software development.
Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno
DATE1
2003 Hardware/Software Design Space Exploration for a Reconfigurable Processor
Alberto La Rosa, Luciano Lavagno, Claudio Passerone
DATE1
2001 A software development tool chain for a reconfigurable processor
abstract
Article Share on A software development tool chain for a reconfigurable processor Authors: Alberto La Rosa Dipartimento di Elettronica, Politecnico di Torino, Italy Dipartimento di Elettronica, Politecnico di Torino, ItalyView Profile , Luciano Lavagno Dipartimento di Elettronica, Politecnico di Torino, Italy Dipartimento di Elettronica, Politecnico di Torino, ItalyView Profile , Claudio Passerone Dipartimento di Elettronica, Politecnico di Torino, Italy Dipartimento di Elettronica, Politecnico di Torino, ItalyView Profile Authors Info & Claims CASES '01: Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systemsNovember 2001Pages 93–98https://doi.org/10.1145/502217.502232Published:16 November 2001Publication History 16citation670DownloadsMetricsTotal Citations16Total Downloads670Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Alberto La Rosa, Luciano Lavagno, Claudio Passerone
CASES1