A hybrid-redundant multiprocessor is proposed in which each processing unit and each memory module is triplicated for purposes of error detection and momentary error masking Reconfiguration allows spare units to replace failed units and allows surviving units to regroup after spares have been exhausted. An arbitrary number of processing units and memory modules can be accommodated. A hybrid-redundant bus system interconnects the processors and memories, where the initial redundancy of the buses is a design parameter. A specialized circuit called a bus guardian unit (BGU) is employed in numerous places to control reconfiguration and testing in such a way as to eliminate susceptibility to failure events that occur in one module at a time. Considerable emphasis is placed on dynamic testing. This approach is briefly compared to other fault-tolerant computer systems.

A distributed fault-tolerant information processing system is proposed, comprising a central multiprocessor, dedicated local processors, and multiplexed input–output buses connecting them together. The processors in the multiprocessor are duplicated for error detection, which is felt to be less expensive than using coded redundancy of comparable effectiveness. Error recovery is made possible by a triplicated scratchpad memory in each processor. The main multiprocessor memory uses replicated memory for error detection and correction. Local processors use any of three conventional redundancy techniques: voting, duplex pairs with backup, and duplex pairs in independent subsystems.

Some logical aspects of a digital computer for a space vehicle are described, and the evolution of its logical design is traced. The intended application and the characteristics of the computer's ancestry form a framework for the design, which is filled in by accumulation of the many decisions made by its designers. This paper deals with the choice of word length, number system, instruction set, memory addressing, and problems of multiple precision arithmetic. The computer is a parallel, single address machine with more than 10,000 words of 16 bits. Such a short word length yields advantages of efficient storage and speed, but at a cost of logical complexity in connection with addressing, instruction selection, and multiple-precison arithmetic.

The high-order probabilities of element sequences can be determined from a sample of linear structures and can be used for synthesis of new structures. From theoretical considerations one can identify the qualitative conditions for satisfactory output. The theoretical concepts can be tested and quantitative parameters determined by experiment. Such an experiment has been performed by analyzing written music and by testing the analysis through the synthesis of new musical compositions, using a digital computer. A sample of 37 melodies was analyzed for the probabilities of the elements, element pairs (digrams), trigrams, and so on to the eighth order. The tables derived were used for the synthesis of original melodies by a random process. The theory and the experimental verification are considered in detail. The experimental results presented include comparative statistics of the successful syntheses using each of the eight orders of analysis, examples of melodies generated by low, medium, and high-order synthesis, and confirmation of degeneracy and other effects predicted by the theory.