This poster evaluated a four-month online professional development program helping seven Southeast Asian teachers from Lao PDR, Thailand, Cambodia and Indonesia embed Computational Thinking (CT) and Universal Design for Learning (UDL) into their lesson plans. Through structured sessions and iterative planning cycles, participants co-created, implemented and revised lessons. Qualitative analysis of their plans, reflections and community discussions showed marked growth: early drafts featured only basic CT and UDL elements, whereas later versions incorporated advanced CT skills (decomposition, data analysis, pseudocoding) and UDL strategies (multiple means of engagement, representation and expression). These results suggest that reflective, collaborative professional development (PD) can boost teachers’ competence and confidence in delivering inclusive, computation-rich instruction.

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.

Persons with severe motor impairments depend heavily upon caregivers for the performance of everyday tasks. Ongoing work is exploring the potential of giving motor-impaired users control of semi-autonomous assistive mobile manipulators to enable them to perform some self-care tasks such as scratching or shaving. Because these users are less able to escape a robot malfunction, or operate a traditional run-stop, physical human-robot interaction poses safety risks. We review approaches to safety in assistive robotics with a focus on accessible run-stops, and propose wincing as an accessible gesture for activating a run-stop device. We also present the wouse, a novel device for detecting wincing from skin movement near the eye, consisting of optical mouse components mounted near a user's temple via safety goggles. Using this device, we demonstrate a complete system to run-stop a Willow Garage PR2 robot, and perform two preliminary user studies. The first study examines discrimination of wincing from self-produced facial expressions. The results indicate the possibility for discrimination, though variability between users and inconsistent detection of skin movement remain significant challenges. The second experiment examines discrimination of wincing from external mechanical manipulations of the face during self-care tasks. The results indicate that the wouse, using a classifier trained with data from the first experiment, can be used during face-manipulation tasks. The device produced no false positives, but succeeded in correctly identifying wincing events in only two of four subjects.

This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total power without any performance loss. This paper describes the technique used for programmable power management, and describes the experimental evaluation that led to the choice of regions in these architectures. The memory architecture is also explored by adding heterogeneous memory mapping to the FPGA Modeling Toolkit, and used to explore LUT based memory structures. The ALM structure provides more inputs than required for a simple 6 LUT, which can be used with simple modifications to efficiently support simple dual-ported LUT based RAM. Replacing the Stratix-II" small memory blocks with LUT RAM and changing the size of other two memories is shown to reduce overall core area across a set of benchmark designs.

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. The paper surveys existing solutions for SoC and analyses the suitability for rSoC application. It also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.