We introduce a network-based problem detection framework for distributed systems, which includes a data-mining method for discovering dynamic dependencies among distributed services from transaction data collected from network, and a novel problem detection method based on the discovered dependencies. From observed containments of transaction execution time periods, we estimate the probabilities of accidental and non-accidental containments, and build a competitive model for discovering direct dependencies by using a model estimation method based on the online EM algorithm. Utilizing the discovered dependency information, we also propose a hierarchical problem detection framework, where microscopic dependency information is incorporated with a macroscopic anomaly metric that monitors the behavior of the system as a whole. This feature is made possible by employing a network-based design which provides overall information of the system without any impact on the performance.

This paper describes a topological routing path search algorithm embedded in our rubber-band-based autorouter for single-layer printed circuit boards. The algorithm searches for a topological path that is guaranteed to be transformable into a physical wire satisfying design rules. Topological path search algorithms used in existing autorouters verify design rules only locally and approximately. However, it is preferable to satisfy design rules exactly in the global routing phase, especially for routing a densely wired printed circuit board. We propose a method for incrementally verifying design rules during the topological routing path search and describe several improvements to the algorithm that reduce the overhead of the routability test and suppress combinatorial explosion. We also discuss the practical feasibility of the proposed algorithm on the basis of the results of experiments using several printed circuit boards.

This paper describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gao's algorithm by resolving its bottleneck related to generation of fan-shaped forbidden regions along a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through which wires can pass. From the experiments we obtained the result that the average CPU time of the detailed routing algorithm is almost linear to the length of a wire. Since the curvilinear detailed routing is efficient in terms of space usage, the proposed algorithm is important especially for densely wired printed circuit boards such as pin grid array packages, ball grid array packages, and multichip modules. We can also expect improvements on the electrical characteristics and the production yield by applying wire-spreading and wire-fattening to them.

This article describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gao's algorithm by resolving its bottleneck related to generation of fan-shaped forbidden regions along a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through which wires can pass. From the experiments we obtained the result that the average CPU time of the detailed routing algorithm is almost linear to the length of a wire. Since the curvilinear detailed routing is efficient in terms of space usage, the proposed algorithm is important especially for densely wired printed circuit boards such as PGA packages, BGA packages, and MCMs. We can also expect improvements on the electrical characteristics and the production yield by applying wire-spreading and wire-fattening to them.

The article describes a topological routing path search algorithm embedded in the auto-router for printed circuit boards. The algorithm searches for a topological path that is guaranteed to be transformable into a physical wire satisfying design rules. The authors propose a method for incrementally verifying design rules during topological path search in a graph based on constrained Delaunay triangulation, and describe several improvements to the routing path search algorithm that remedy the overhead of the routability test and avoid combinatorial explosion.